XC5VLX110T-3FFG1136C Xilinx Inc, XC5VLX110T-3FFG1136C Datasheet - Page 9
![IC FPGA VIRTEX-5 110K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX110T-3FFG1136C
Manufacturer Part Number
XC5VLX110T-3FFG1136C
Description
IC FPGA VIRTEX-5 110K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110T-3FFG1136C
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
5455872
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110T-3FFG1136C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Virtex-5 LXT, SXT, TXT, and FXT Platform Features
This section briefly describes blocks available only in LXT, SXT, TXT, and FXT devices.
Tri-Mode (10/100/1000 Mb/s) Ethernet MACs
Virtex-5 LXT, SXT, TXT, and FXT devices contain up to eight
embedded Ethernet MACs, two per Ethernet MAC block.
The blocks have the following characteristics:
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Virtex-5 LXT and SXT Platform Features
This section briefly describes blocks available only in LXT and SXT devices.
RocketIO GTP Transceivers
4 - 24 channel RocketIO GTP transceivers capable of
running 100 Mb/s to 3.75 Gb/s.
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DS100 (v5.0) February 6, 2009
Product Specification
Designed to the IEEE 802.3-2002 specification
UNH-compliance tested
RGMII/GMII Interface with SelectIO or SGMII interface
when used with RocketIO transceivers
Half or full duplex
Supports Jumbo frames
1000 Base-X PCS/PMA: When used with RocketIO
GTP transceiver, can provide complete 1000 Base-X
implementation on-chip
DCR-bus connection to microprocessors
Full clock and data recovery
8/16-bit or 10/20-bit datapath support
Optional 8B/10B or FPGA-based encode/decode
Integrated FIFO/elastic buffer
Channel bonding and clock correction support
Embedded 32-bit CRC generation/checking
Integrated comma-detect or A1/A2 detection
Programmable pre-emphasis (AKA transmitter
equalization)
R
www.xilinx.com
Integrated Endpoint Blocks for PCI Express
Virtex-5 LXT, SXT, TXT, and FXT devices contain up to four
integrated Endpoint blocks. These blocks implement
Transaction Layer, Data Link Layer, and Physical Layer
functions to provide complete PCI Express Endpoint
functionality with minimal FPGA logic utilization. The blocks
have the following characteristics:
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Virtex-5 FPGA RocketIO GTP transceivers are further
discussed in the Virtex-5 FPGA RocketIO GTP Transceiver
User Guide.
Compliant with the PCI Express Base Specification 1.1
Works in conjunction with RocketIO transceivers to
provide complete endpoint functionality
1, 4, or 8 lane support per block
Programmable transmitter output swing
Programmable receiver equalization
Programmable receiver termination
Embedded support for:
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Built-in PRBS generator/checker
Out of Band (OOB) signalling: Serial ATA
Beaconing, electrical idle, and PCI Express receiver
detection
Virtex-5 Family Overview
9