XC5VLX110T-1FF1738I Xilinx Inc, XC5VLX110T-1FF1738I Datasheet - Page 203
![IC FPGA VIRTEX-5 110K 1738FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX110T-1FF1738I
Manufacturer Part Number
XC5VLX110T-1FF1738I
Description
IC FPGA VIRTEX-5 110K 1738FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110T-1FF1738I
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
5455872
Number Of I /o
680
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1738-BBGA, FCBGA
For Use With
HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1738-500-G - BOARD DEV VIRTEX 5 FF1738
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110T-1FF1738I
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
- Current page: 203 of 385
- Download datasheet (14Mb)
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Timing Characteristics
Figure 5-26
X-Ref Target - Figure 5-26
•
•
•
At time T
CE input of the slice register.
At time T
become valid-High at the D input of the slice register and is reflected on either the
AQ, BQ, CQ, or DQ pin at time T
At time T
becomes valid-High, resetting the slice register. This is reflected on the AQ, BQ, CQ,
or DQ pin at time T
illustrates the general timing characteristics of a Virtex-5 FPGA slice.
CEO
DICK
SRCK
AQ/BQ/CQ/DQ
AX/BX/CX/DX
before clock event (1), the clock-enable signal becomes valid-High at the
SR (RESET)
Figure 5-26: General Slice Timing Characteristics
before clock event (1), data from either AX, BX, CX, or DX inputs
before clock event (3), the SR signal (configured as synchronous reset)
(DATA)
(OUT)
CKO
CLK
CE
www.xilinx.com
after clock event (3).
1
CKO
T
T
CEO
DICK
after clock event (1).
T
CKO
2
3
CLB / Slice Timing Models
T
ug190_5_26_050506
SRCK
T
CKO
203
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