XC5VSX95T-1FFG1136C Xilinx Inc, XC5VSX95T-1FFG1136C Datasheet - Page 102

• Manufacturer Part Number: XC5VSX95T-1FFG1136C
• Description: IC FPGA VIRTEX-5 95K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX95T-1FFG1136C

• Total Ram Bits: 8994816
• Number Of Logic Elements/cells: 94208
• Number Of Labs/clbs: 7360
• Number Of I /o: 640
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7360
• No. Of Macrocells: 95000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 640
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Phase-Locked Loops (PLLs)
102
Counter Control
The PLL output counters provide a wide variety of synthesized clock using a combination
of DIVIDE, DUTY_CYCLE, and PHASE.
impact the counter output.
The top waveform represents either the output from the VCO in PLL mode.
X-Ref Target - Figure 3-6
DUTY_CYCLE = 0.75
DUTY_CYCLE = 0.33
DUTY_CYCLE = 0.5
DUTY_CYCLE = 0.5
DUTY_CYCLE = 0.5
DUTY_CYCLE = 0.5
DUTY_CYCLE = 0.5
Counter Clock Input
PHASE = 180
PHASE = 180
PHASE = 360
DIVIDE = 2
PHASE = 0
DIVIDE = 2
DIVIDE = 2
DIVIDE = 1
PHASE = 0
DIVIDE = 1
DIVIDE = 3
PHASE = 0
DIVIDE = 3
PHASE = 0
(VCO)
Figure 3-6: Output Counter Clock Synthesis Examples
www.xilinx.com
Figure 3-6
illustrates how the counter settings
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
UG190_3_06_041406