XC4VFX100-10FFG1152I Xilinx Inc, XC4VFX100-10FFG1152I Datasheet - Page 56
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XC4VFX100-10FFG1152I
Manufacturer Part Number
XC4VFX100-10FFG1152I
Description
IC FPGA VIRTEX-4FX 100K 1152FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX100-10FFG1152I
Number Of Logic Elements/cells
94896
Number Of Labs/clbs
10544
Total Ram Bits
6930432
Number Of I /o
576
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1152-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 2: Digital Clock Managers (DCMs)
56
•
Figure 2-1
including all DCM locations.
Virtex-4 device.
direct mode the phase can be dynamically and repetitively moved forward and
backwards by the value of one DCM_TAP. See the DCM Timing Parameters section in
the
Dynamic Reconfiguration
There is a bus connection to the DCM to change DCM attributes without reconfiguring
the rest of the device. For more information, see the Dynamic Reconfiguration chapter
of the
The DADDR[6:0], DI[15:0], DWE, DEN, DCLK inputs and DO[15:0], and DRDY
outputs are available to dynamically reconfigure select DCM functions. With dynamic
reconfiguration, DCM attributes can be changed to select a different phase shift,
multiply (M) or divide (D) from the currently configured settings.
Virtex-4 Data
Virtex-4 Configuration
shows a simplified view of the Virtex-4 FPGA center column resources
Sheet.
www.xilinx.com
Table 2-1
Figure 2-1: DCM Location
Guide.
BUFGCTRLs
BUFGCTRLs
(Bottom Half)
(Bottom Half)
(Bottom Half)
summarizes the availability of DCMs in each
(Top Half)
(Top Half)
(Top Half)
PMCDs
PMCDs
DCMs
DCMs
I/Os
I/Os
Center Column
Virtex-4 FPGA
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
UG070_2_01_030708
R
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