XC5VLX85-3FFG1153C Xilinx Inc, XC5VLX85-3FFG1153C Datasheet - Page 243

• Manufacturer Part Number: XC5VLX85-3FFG1153C
• Description: IC FPGA VIRTEX-5 85K 1153FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX85-3FFG1153C

• Number Of Logic Elements/cells: 82944
• Number Of Labs/clbs: 6480
• Total Ram Bits: 3538944
• Number Of I /o: 560
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1153-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
LVDCI (Low Voltage Digitally Controlled Impedance)
Table 6-8
standard.
Table 6-8: Allowed Attributes for the LVCMOS12 I/O Standard
Using these I/O buffers configures the outputs as controlled impedance drivers. The
receiver of LVDCI is identical to a LVCMOS receiver. Some I/O standards, such as LVTTL,
LVCMOS, etc., must have a drive impedance that matches the characteristic impedance of
the driven line. Virtex-5 devices provide a controlled impedance output driver to provide
series termination without external source termination resistors. The impedance is set by
the common external reference resistors, with resistance equal to the trace characteristic
impedance, Z
Sample circuits illustrating both unidirectional and bidirectional termination techniques
for a controlled impedance driver are shown in
standards supporting a controlled impedance driver are: LVDCI_15, LVDCI_18,
LVDCI_25, and LVDCI_33.
X-Ref Target - Figure 6-31
X-Ref Target - Figure 6-32
IOSTANDARD
DRIVE
SLEW
Figure 6-31: Controlled Impedance Driver with Unidirectional Termination
Figure 6-32: Controlled Impedance Driver with Bidirectional Termination
R 0 = R VRN = R VRP = Z 0
Attributes
details the allowed attributes that can be applied to the LVCMOS12 I/O
LVDCI
R 0 = R VRN = R VRP = Z 0
0
.
LVDCI
www.xilinx.com
IOB
IOB
IBUF/IBUFG
LVCMOS12
UNUSED
UNUSED
Specific Guidelines for I/O Supported Standards
Z 0
Z 0
Figure 6-31
OBUF/OBUFT
{FAST, SLOW}
LVCMOS12
Primitives
2, 4, 6, 8
IOB
IOB
R 0 = R VRN = R VRP = Z 0
and
LVDCI
Figure
LVDCI
ug190_6_28_022806
6-32. The DCI I/O
{FAST, SLOW}
LVCMOS12
ug190_6_29_022806
2, 4, 6, 8
IOBUF
243