XC5VLX85-3FF1153C Xilinx Inc, XC5VLX85-3FF1153C Datasheet - Page 118
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XC5VLX85-3FF1153C
Manufacturer Part Number
XC5VLX85-3FF1153C
Description
IC FPGA VIRTEX-5 85K 1153FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX85-3FF1153C
Number Of Logic Elements/cells
82944
Number Of Labs/clbs
6480
Total Ram Bits
3538944
Number Of I /o
560
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1153-BBGA, FCBGA
For Use With
HW-AFX-FF1153-500-G - BOARD DEV VIRTEX 5 FF1153
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX85-3FF1153C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 4: Block RAM
118
WRITE_FIRST or Transparent Mode (Default)
READ_FIRST or Read-Before-Write Mode
NO_CHANGE Mode
In WRITE_FIRST mode, the input data is simultaneously written into memory and stored
in the data output (transparent write), as shown in
correspond to latch mode when the optional output pipeline register is not used.
X-Ref Target - Figure 4-2
In READ_FIRST mode, data previously stored at the write address appears on the output
latches, while the input data is being stored in memory (read before write). The waveforms
in
used.
X-Ref Target - Figure 4-3
In NO_CHANGE mode, the output latches remain unchanged during a write operation.
As shown in
operation on the same port. These waveforms correspond to latch mode when the optional
output pipeline register is not used.
Figure 4-3
ADDR
ADDR
CLK
CLK
WE
WE
DO
DO
EN
EN
DI
DI
Figure
correspond to latch mode when the optional output pipeline register is not
Disabled
Disabled
0000
0000
4-4, data output remains the last read data and is unaffected by a write
Figure 4-2: WRITE_FIRST Mode Waveforms
Figure 4-3: READ_FIRST Mode Waveforms
XXXX
XXXX
www.xilinx.com
aa
aa
Read
Read
MEM(aa)
MEM(aa)
bb
MEM(bb)=1111
1111
bb
MEM(bb)=1111
1111
Write
Write
old MEM(bb)
1111
Figure
2222
cc
2222
cc
MEM(cc)=2222
MEM(cc)=2222
4-2. These waveforms
Write
Write
old MEM(cc)
2222
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
dd
dd
ug190_4_04_032206
ug190_4_03_032206
XXXX
XXXX
Read
Read
MEM(dd)
MEM(dd)
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