XC5VLX85-2FFG1153I Xilinx Inc, XC5VLX85-2FFG1153I Datasheet - Page 4
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XC5VLX85-2FFG1153I
Manufacturer Part Number
XC5VLX85-2FFG1153I
Description
IC FPGA VIRTEX-5 85K 1153FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX85-2FFG1153I
Number Of Logic Elements/cells
82944
Number Of Labs/clbs
6480
Total Ram Bits
3538944
Number Of I /o
560
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1153-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX85-2FFG1153I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Virtex-5 Family Overview
Digitally Controlled Impedance (DCI)
Active I/O Termination
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Configuration
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Advanced Flip-Chip Packaging
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System Blocks Specific to the LXT, SXT, TXT, and FXT Devices
Integrated Endpoint Block for PCI Express
Compliance
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4
Optional series or parallel termination
Temperature and voltage compensation
Makes board layout much easier
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Support for platform Flash, standard SPI Flash, or
standard parallel NOR Flash configuration
Bitstream support with dedicated fallback
reconfiguration logic
256-bit AES bitstream decryption provides intellectual
property security and prevents design copying
Improved bitstream error detection/correction capability
Auto bus width detection capability
Partial Reconfiguration via ICAP port
Pre-engineered packaging technology for proven
superior signal integrity
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Reduces SSO induced noise by up to 7x
Pb-Free and standard packages
Works in conjunction with RocketIO GTP transceivers
(LXT and SXT) and GTX transceivers (TXT and FXT)
to deliver full PCI Express Endpoint functionality with
minimal FPGA logic utilization.
Compliant with the PCI Express Base Specification 1.1
PCI Express Endpoint block or Legacy PCI Express
Endpoint block
x8, x4, or x1 lane width
Power management support
Block RAMs used for buffering
Fully buffered transmit and receive
Management interface to access PCI Express
configuration space and internal configuration
Supports the full range of maximum payload sizes
Up to 6 x 32 bit or 3 x 64 bit BARs (or a combination of
32 bit and 64 bit)
Reduces resistors
Places termination in the ideal location, at the signal
source or destination
Minimized inductive loops from signal to return
Optimal signal-to-PWR/GND ratios
www.xilinx.com
System Monitor
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65-nm Copper CMOS Process
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Tri-Mode Ethernet Media Access Controller
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On-Chip temperature measurement (±4°C)
On-Chip power supply measurement (±1%)
Easy to use, self-contained
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User accessible 10-bit 200kSPS ADC
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Up to 17 external analog input channels supported
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Full access from fabric or JTAG TAP to System Monitor
Fully operational prior to FPGA configuration and
during device power down (access via JTAG TAP only)
1.0V Core Voltage
12-layer metal provides maximum routing capability
and accommodates hard-IP immersion
Triple-oxide technology for proven reduced static power
consumption
Designed to the IEEE 802.3-2002 specification
Operates at 10, 100, and 1,000 Mb/s
Supports tri-mode auto-negotiation
Receive address filter (5 address entries)
Fully monolithic 1000Base-X solution with RocketIO
GTP transceivers
Supports multiple external PHY connections (RGMII,
GMII, etc.) interfaces through soft logic and SelectIO
resources
Supports connection to external PHY device through
SGMII using soft logic and RocketIO GTP transceivers
Receive and transmit statistics available through
separate interface
Separate host and client interfaces
Support for jumbo frames
Support for VLAN
Flexible, user-configurable host interface
Supports IEEE 802.3ah-2004 unidirectional mode
No design required for basic operation
Autonomous monitoring of all on-chip sensors
User programmable alarm thresholds for on-chip
sensors
Automatic calibration of offset and gain error
DNL = ±0.9 LSBs maximum
0V to 1V input range
Monitor external sensors e.g., voltage, temperature
General purpose analog inputs
DS100 (v5.0) February 6, 2009
Product Specification
R