XC5VLX85T-3FF1136C Xilinx Inc, XC5VLX85T-3FF1136C Datasheet - Page 42
![IC FPGA VIRTEX-5 85K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX85T-3FF1136C
Manufacturer Part Number
XC5VLX85T-3FF1136C
Description
IC FPGA VIRTEX-5 85K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX85T-3FF1136C
Number Of Logic Elements/cells
82944
Number Of Labs/clbs
6480
Total Ram Bits
3981312
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
122-1586 - BOARD EVAL FOR VIRTEX-5 ML555HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX85T-3FF1136C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 1: Clock Resources
42
Regional Clock Buffer - BUFR
X-Ref Target - Figure 1-19
The regional clock buffer (BUFR) is another clock buffer available in Virtex-5 devices.
BUFRs drive clock signals to a dedicated clock net within a clock region, independent from
Clock Capable I/O
Clock Capable I/O
Clock Capable I/O
Clock Capable I/O
Not all available BUFIOs are shown.
Figure 1-19: BUFIO Driving I/O Logic In a Single Clock Region
P
P
N
N
P
N
P
N
www.xilinx.com
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
BUFIO
BUFIO
BUFR
BUFR
To Adjacent
Region
To Adjacent
Region
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ug190_1_19_060706
To Fabric
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