XC5VLX85-3FF676C Xilinx Inc, XC5VLX85-3FF676C Datasheet - Page 319
![IC FPGA VIRTEX-5 85K 676FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX85-3FF676C
Manufacturer Part Number
XC5VLX85-3FF676C
Description
IC FPGA VIRTEX-5 85K 676FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX85-3FF676C
Number Of Logic Elements/cells
82944
Number Of Labs/clbs
6480
Total Ram Bits
3538944
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA, FCBGA
For Use With
HW-AFX-FF676-500-G - BOARD DEV VIRTEX 5 FF676
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Combinatorial Input Path
Input DDR Overview (IDDR)
OPPOSITE_EDGE Mode
Table 7-2: Truth Table when SRVAL = 1
The SRVAL attributes can be set individually for each storage element in the ILOGIC block,
but the choice of synchronous or asynchronous set/reset (SRTYPE) can not be set
individually for each storage element in the ILOGIC block.
The following sections discuss the various resources within the ILOGIC blocks. All
connections between the ILOGIC resources are managed in Xilinx software.
The combinatorial input path is used to create a direct connection from the input driver to
the FPGA fabric. This path is used by software automatically when:
1.
2.
Virtex-5 devices have dedicated registers in the ILOGIC to implement input double-data-
rate (DDR) registers. This feature is used by instantiating the IDDR primitive.
There is only one clock input to the IDDR primitive. Falling edge data is clocked by a
locally inverted version of the input clock. All clocks feeding into the I/O tile are fully
multiplexed, i.e., there is no clock sharing between ILOGIC and OLOGIC blocks. The
IDDR primitive supports the following modes of operation:
•
•
•
The SAME_EDGE and SAME_EDGE_PIPELINED modes are the same as for the Virtex-4
architecture. These modes allow designers to transfer falling edge data to the rising edge
domain within the ILOGIC block, saving CLB and clock resources, and increasing
performance. These modes are implemented using the DDR_CLK_EDGE attribute. The
following sections describe each of the modes in detail.
A traditional input DDR solution, or OPPOSITE_EDGE mode, is accomplished via a single
input in the ILOGIC. The data is presented to the fabric via the output Q1 on the rising
edge of the clock and via the output Q2 on the falling edge of the clock. This structure is
similar to the Virtex-II, Virtex-II Pro, and Virtex-4 FPGA implementation.
the timing diagram of the input DDR using the OPPOSITE_EDGE mode.
SR
0
0
1
1
There is a direct (unregistered) connection from input data to logic resources in the
FPGA fabric.
The "pack I/O register/latches into IOBs" is set to OFF.
OPPOSITE_EDGE mode
SAME_EDGE mode
SAME_EDGE_PIPELINED mode
REV
0
1
0
1
NOP
Set
Reset
Reset
www.xilinx.com
Function
ILOGIC Resources
Figure 7-2
shows
319
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