XC5VSX50T-2FFG665I Xilinx Inc, XC5VSX50T-2FFG665I Datasheet - Page 171
XC5VSX50T-2FFG665I
Manufacturer Part Number
XC5VSX50T-2FFG665I
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX50T-2FFG665I
Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX50T-2FFG665I
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Legal Block RAM and FIFO Combinations
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Block RAM ECC VHDL and Verilog Templates
VHDL and Verilog templates are available in the Libraries Guide.
The block RAM–FIFO combinations shown in
RAMB36 primitive. When placing block RAM and FIFO primitives in the same location,
the FIFO must occupy the lower port.
X-Ref Target - Figure 4-33
RAMB18
RAMB18
Figure 4-33: Legal Block RAM and FIFO Combinations
www.xilinx.com
RAMB18SDP
RAMB18SDP
Legal Block RAM and FIFO Combinations
Figure 4-33
RAMB18
FIFO18
are supported in a single
RAMB18SDP
FIFO18_36
ug0190_4_35_050208
171
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