XC5VLX110-1FF1153C Xilinx Inc, XC5VLX110-1FF1153C Datasheet - Page 351
XC5VLX110-1FF1153C
Manufacturer Part Number
XC5VLX110-1FF1153C
Description
IC FPGA VIRTEX-5 110K 1153FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110-1FF1153C
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
4718592
Number Of I /o
800
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1153-BBGA, FCBGA
For Use With
HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1153-500-G - BOARD DEV VIRTEX 5 FF1153
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110-1FF1153C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
X-Ref Target - Figure 7-29
Clock Event 1
•
•
Clock Event 2
•
Clock Event 9
•
TCE
At time T
High at the TCE input of the 3-state ODDR register, enabling them for incoming data.
Care must be taken to toggle the TCE signal of the 3-state ODDR between the rising
edges and falling edges of CLK as well as meeting the register setup-time relative to
both clock edges.
At time T
becomes valid-High at the T1 input of 3-state register and is reflected on the TQ
output at time T
At time T
becomes valid-High at the T2 input of 3-state register and is reflected on the TQ
output at time T
At time T
as synchronous reset in this case) becomes valid-High resetting 3-state Register,
reflected at the TQ output at time T
in this case) and resetting 3-state Register, reflected at the TQ output at time T
Clock Event 10 (no change at the TQ output in this case).
SR
TQ
CLK
T1
T2
T OCKQ
Figure 7-29: OLOGIC ODDR 3-State Register Timing Characteristics
OTCECK
OTCK
OTCK
OSRCK
1
T OTCECK
T OTCK
before Clock Event 1 (rising edge of CLK), the 3-state signal T1
before Clock Event 2 (falling edge of CLK), the 3-state signal T2
OCKQ
OCKQ
before Clock Event 9 (rising edge of CLK), the SR signal (configured
before Clock Event 1, the 3-state clock enable signal becomes valid-
2
www.xilinx.com
after Clock Event 1.
after Clock Event 2 (no change at the TQ output in this case).
3
T OTCK
4
RQ
5
after Clock Event 9 (no change at the TQ output
6
T OSRCK
7
8
9
OLOGIC Resources
10
T RQ
ug190_7_24_041106
11
RQ
after
351
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