XC5VLX85-1FFG676I Xilinx Inc, XC5VLX85-1FFG676I Datasheet - Page 334
![IC FPGA VIRTEX-5 85K 676FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX85-1FFG676I
Manufacturer Part Number
XC5VLX85-1FFG676I
Description
IC FPGA VIRTEX-5 85K 676FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX85-1FFG676I
Number Of Logic Elements/cells
82944
Number Of Labs/clbs
6480
Total Ram Bits
3538944
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
XC5VLX85-1FFG676I
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10 000
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Chapter 7: SelectIO Logic Resources
X-Ref Target - Figure 7-11
334
CLK
CLK
Q1
Q2
D1
D2
T1
T2
Figure 7-11:
ODDR
ODDR
IDDR
Two cases that use the bidirectional IODELAY functionality are important for a given I/O
pin. The first case uses bidirectional IODELAY when the I/O is an output being switched
to an input.
set by the TSCONTROL net coming from the ODDR flip-flop. This controls the selection of
MUXes E and F for the IOB input path and IDELAY_VALUE, respectively. Additionally,
the OBUF is 3-stated.
IODELAY and IOB in Input Mode when 3-state is Disabled
Figure 7-11
DATAOUT
ODATAIN
IODELAY
Delay
Chain
shows the IOB and IODELAY moving toward the input mode as
www.xilinx.com
TSCONTROL
MUX E
MUX F
T
ODELAY_VALUE
IDELAY_VALUE
ODATAIN
IDATAIN
OBUF
IBUF
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
IOB
IODELAY_02_082107
PAD
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