XC4VFX60-11FFG1152C Xilinx Inc, XC4VFX60-11FFG1152C Datasheet - Page 177
XC4VFX60-11FFG1152C
Manufacturer Part Number
XC4VFX60-11FFG1152C
Description
IC FPGA VIRTEX-4 FX 60K 1152FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX60-11FFG1152C
Number Of Logic Elements/cells
56880
Number Of Labs/clbs
6320
Total Ram Bits
4276224
Number Of I /o
576
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-BBGA, FCBGA
For Use With
HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Price
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Part Number:
XC4VFX60-11FFG1152C
Manufacturer:
AVX
Quantity:
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Part Number:
XC4VFX60-11FFG1152C
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Solution Summary
R
Design Files
All the necessary files required for the above design are contained in a ZIP archive
downloadable from the Xilinx website at:
Open the ZIP archive and extract FIFO16_solution3.zip.
The following criteria can be used to choose a particular solution for the design.
•
•
•
https://secure.xilinx.com/webreg/clickthrough.do?cid=30163
“Solution 1: Synchronous/Asynchronous Clock Work-Arounds”
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“Solution 2: Work-Around Using a Third Fast Clock”
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♦
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“Solution 3: FIFO Flag Generator Using Gray Code”
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Design is currently supported in the CORE Generator tool
Design is required to run at the maximum FIFO16 clock rates
Exact values are required for the ALMOSTEMPTY and ALMOSTFULL Flags
Resource utilization is more than that for Solution 2 and Solution 3 (see Solution 1
for details)
Continuous RDCLK and WRCLK are available after RST
Smallest resource utilization is required
RDCLK and WRCLK needs to be intermittently stopped after RST
Design is not required to run at the maximum FIFO16 clock rates (see Solution 2
for more details)
The generation of a third continuous fast clock is feasible
ALMOSTEMPTY and ALMOSTFULL flags can be delayed by from 1 to 2 RDCLK
or WRCLK periods, respectively
Design is required to run at the maximum FIFO16 clock rates
Resource utilization smaller than Solution 1 is required
RDCLK and WRCLK needs to be intermittently stopped after RST
ALMOSTEMPTY and ALMOSTFULL flags need not be exact and can be within a
range.
www.xilinx.com
FIFO16 Error Condition and Work-Arounds
should be used if:
should be used if:
should be used if:
177
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