XC4VFX60-10FFG1152I Xilinx Inc, XC4VFX60-10FFG1152I Datasheet - Page 81

• Manufacturer Part Number: XC4VFX60-10FFG1152I
• Description: IC FPGA VIRTEX-4 FX 60K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-10FFG1152I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 576
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Dynamic Reconfiguration
R
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The Dynamic Reconfiguration Ports (DRPs) can update the initial DCM settings without
reloading a new bitstream to the FPGA. The
information on using DRPs. Specific to the DCM, DRPs can perform the following
functions:
•
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The following steps are required when using DRPs to load new M and D values:
•
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The phase-shifting (DPS) function in the DCM requires the CLKFB for delay
adjustment.
Because CLKFB must be from CLK0, the DLL output is used. The minimum CLKIN
frequency for the DPS function is determined by DLL frequency mode.
Allow dynamic adjustment of CLKFX_MULTIPLY(M) and CLKFX_DIVIDE(D) value
to produce a new CLKFX frequency.
Allow dynamic adjustment of PHASE_SHIFT value to produce a new phase shift.
This feature can be used with the fixed, variable, or direct phase-shift modes to set a
specific phase-shift value.
Subtract the desired M and D values by one. For example, if the desired M/D = 9/4,
then load M/D = 8/3.
Hold DCM in reset (assert RST signal) and release it after the new M and D values are
written. The CLKFX outputs can be used after LOCKED is asserted High again.
www.xilinx.com
Virtex-4 Configuration Guide
DCM Design Guidelines
provides more
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