XC4VFX60-10FFG1152C Xilinx Inc, XC4VFX60-10FFG1152C Datasheet - Page 17

• Manufacturer Part Number: XC4VFX60-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 60K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-10FFG1152C

• Total Ram Bits: 4276224
• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Number Of I /o: 576
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• No. Of Logic Blocks: 6656
• No. Of Macrocells: 56880
• Family Type: Virtex-4
• No. Of Speed Grades: 10
• No. Of I/o's: 576
• Clock Management: DCM
• Core Supply: RoHS Compliant
• Package: 1152FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 56880
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 576
• Ram Bits: 4276224
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 25: RocketIO Receiver Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
Notes:
1.
2.
3.
4.
5.
Serial data rate, -10
Serial data rate, -11
XAUI Receive Jitter Tolerance (8B/10B CJPAT)
General Receive Jitter Tolerance
RXUSRCLK frequency
RXUSRCLK2 frequency
RXUSRCLK duty cycle
RXUSRCLK2 duty cycle
Differential input skew
Differential receive input sensitivity
On-chip AC coupling corner frequency
Signal detect response time
Input capacitance at the Die
Excess capacitance at the solder ball
Receive Deterministic Jitter Tolerance
Receive Total Jitter Tolerance
Receive Sinusoidal Jitter Tolerance
Receive deterministic jitter tolerance
Sinusoidal jitter tolerance
UI = Unit Interval
Using receiver equalization setting of 111 (14 dB).
ACDR = Analog CDR and DCDR = Digital CDR.
Deterministic jitter (DJ) is composed of 75% ISI + 25% high frequency
sinusoidal jitter (SJ).
Deterministic Jitter (DJ) composed of ISI + 0.10 UI of high frequency SJ +
0.15 UI of RJ.
Description
(2)
RXSIGDET
T
T
T
Symbol
DJTOL
T
T
T
T
SJTOL
T
TJTOL
C
F
F
V
T
RX2DC
ISKEW
C
DJTOL
SJTOL
T
RXDC
BALL
GRX
GRX
RX2
EYE
DIE
RX
(2)
(2,4)
(6)
(7)
Responsetime
Rate (Gb/s) Mode
Rate (Gb/s)
For slower speed grades = MaxDataRate/32
3.125
0.622
4.25
4.25
1.25
1.25
1.25
www.xilinx.com
3.125
3.125
3.125
3.125
3.125
3.125
0.622
6.5
5.0
6.5
5.0
2.5
1.25
1.25
1.25
2.5
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
(5)
(5)
(9)
(9)
(8)
(5)
(9)
(8)
(8)
(8)
(8)
(8)
6.
7.
8.
9.
Conditions
Mode
ACDR
ACDR
ACDR
ACDR
ACDR
ACDR
ACDR
ACDR
ACDR
ACDR
ACDR
DCDR
DCDR
DCDR
ACDR
ACDR
ACDR
ACDR
ACDR
ACDR
DCDR
DCDR
DCDR
Sum of DJ, random jitter (RJ) of at least 0.55 UI, and sinusoidal jitter
as defined by mask in IEEE Std 802.3ae-2002, Figure 47-5.
SJ in addition to 0.55 UI of DJ +RJ.
Jitter frequency = 5 MHz.
Jitter frequency = 10 MHz.
(3)
(3)
Frequency
f = 22.1 kHz
f = 1.875 MHz
f = 20 MHz
PRBS31
PRBS31
PRBS31
PRBS31
Pattern
PRBS7
PRBS7
PRBS7
PRBS7
PRBS7
PRBS7
PRBS7
PRBS7
PRBS7
PRBS7
PRBS7
PRBS7
PRBS7
PRBS7
0.622
0.622
Min
110
40
40
Typ
30
3.125
0.37
0.65
0.10
0.10
0.65
0.65
0.65
0.60
0.55
0.50
0.50
0.40
0.40
0.65
0.65
0.65
0.50
0.50
0.50
0.55
0.35
0.55
Max
250
250
6.5
8.5
60
60
20
Units
Gb/s
Gb/s
UI
UI
MHz
MHz
mV
ps
ns
%
%
fF
fF
(1)
(1)
17