XC6VCX75T-2FFG484I Xilinx Inc, XC6VCX75T-2FFG484I Datasheet - Page 48
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XC6VCX75T-2FFG484I
Manufacturer Part Number
XC6VCX75T-2FFG484I
Description
IC FPGA VIRTEX 6 74K 484FFGBGA
Manufacturer
Xilinx Inc
Series
Virtex™ 6 CXTr
Datasheet
1.XC6VCX75T-1FFG484C.pdf
(52 pages)
Specifications of XC6VCX75T-2FFG484I
Number Of Logic Elements/cells
74496
Number Of Labs/clbs
5820
Total Ram Bits
5750784
Number Of I /o
240
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC6VCX75T-2FFG484I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Virtex-6 CXT Device Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in
Table 61: Global Clock Input Setup and Hold Without MMCM
Table 62: Global Clock Input Setup and Hold With MMCM
Table 63: Clock-Capable Clock Input Setup and Hold With MMCM
DS153 (v1.6) February 11, 2011
Product Specification
Notes:
1.
2.
3.
Notes:
1.
2.
3.
Notes:
1.
2.
3.
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.
T
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.
T
T
Input Setup and Hold Time Relative to Clock-capable Clock Input Signal for LVCMOS25 Standard.
T
T
PSFD
PSMMCMGC
PHMMCMGC
PSMMCMCC
PHMMCMCC
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
IFF = Input Flip-Flop or Latch.
A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0"
is listed, there is no positive hold time.
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
IFF = Input Flip-Flop or Latch.
Use IBIS to determine any duty-cycle distortion incurred using various standards.
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
IFF = Input Flip-Flop or Latch.
Use IBIS to determine any duty-cycle distortion incurred using various standards.
Symbol
Symbol
Symbol
/ T
Table
PHFD
/
/
61. Values are expressed in nanoseconds unless otherwise noted.
Full Delay (Legacy Delay or Default Delay)
Global Clock Input and IFF
No Delay Global Clock Input and IFF
No Delay Clock-capable Clock Input and IFF
with MMCM
Description
Description
Description
(2)
without MMCM
(2)
www.xilinx.com
with MMCM XC6VCX75T
(2)
XC6VCX75T
XC6VCX130T
XC6VCX195T
XC6VCX240T
XC6VCX75T
XC6VCX130T
XC6VCX195T
XC6VCX240T
XC6VCX130T
XC6VCX195T
XC6VCX240T
Device
Device
Device
1.75/–0.01
1.88/–0.11
1.97/–0.14
1.97/–0.14
1.86/–0.28
1.93/–0.28
1.96/–0.27
1.96/–0.27
1.72/–0.22
1.81/–0.21
1.82/–0.20
1.82/–0.20
(1)
(1)
Virtex-6 CXT Family Data Sheet
-2
-2
-2
Speed Grade
Speed Grade
Speed Grade
(1)
1.75/–0.01
1.88/–0.11
1.97/–0.14
1.97/–0.14
1.86/–0.28
1.93/–0.28
1.96/–0.27
1.96/–0.27
1.72/–0.22
1.81/–0.21
1.82/–0.20
1.82/–0.20
-1
-1
-1
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
48