XC5VLX50T-1FF665I Xilinx Inc, XC5VLX50T-1FF665I Datasheet - Page 364
XC5VLX50T-1FF665I
Manufacturer Part Number
XC5VLX50T-1FF665I
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-1FF665I
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 8: Advanced SelectIO Logic Resources
364
Timing Characteristics
Reset Input Timing
Figure 8-8
timing parameter names change for different modes (SDR/DDR). However, the names do
not change when a different bus input width, including when two ISERDES are cascaded
together to form 10 bits. In DDR mode, the data input (D) switches at every CLK edge
(rising and falling).
X-Ref Target - Figure 8-8
Clock Event 1
•
Clock Event 2
•
Clock Event 1
As shown in
the pulse must take two different routes to get to ISERDES0 and ISERDES1, there are
different propagation delays for both paths. The difference in propagation delay is
emphasized. The path to ISERDES0 is very long and the path to ISERDES1 is very short,
such that each ISERDES receives the reset pulse in a different CLK cycle. The internal resets
for both CLK and CLKDIV are reset asynchronously when the RST input is asserted.
At time T
and the ISERDES can sample data.
At time T
sampled at the next positive clock edge.
CLK
CE
D
illustrates an ISERDES timing diagram for the input data to the ISERDES. The
Figure
ISCCK_CE
ISDCK_D
1
Figure 8-8: ISERDES Input Data Timing Diagram
T
8-9, the reset pulse is generated on the rising edge of CLKDIV. Because
ISCCK_CE
, before Clock Event 2, the input data pin (D) becomes valid and is
, before Clock Event 1, the clock enable signal becomes valid-High
www.xilinx.com
2
T
ISDCK_D
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ug190_8_08_100307
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