XC5VLX50-1FF1153I Xilinx Inc, XC5VLX50-1FF1153I Datasheet - Page 59
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XC5VLX50-1FF1153I
Manufacturer Part Number
XC5VLX50-1FF1153I
Description
IC FPGA VIRTEX-5 50K 1153FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-1FF1153I
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
1769472
Number Of I /o
560
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1153-BBGA, FCBGA
Package
1153FCBGA
Family Name
Virtex®-5
Device Logic Units
46080
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
560
Ram Bits
1769472
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1153-500-G - BOARD DEV VIRTEX 5 FF1153HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50-1FF1153I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 78: Input Clock Tolerances
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
4.
Duty Cycle Input Tolerance (in %)
T
T
T
T
T
T
Input Clock Cycle-Cycle Jitter (Low Frequency Mode)
T
T
Input Clock Cycle-Cycle Jitter (High Frequency Mode)
T
T
Input Clock Period Jitter (Low Frequency Mode)
T
T
Input Clock Period Jitter (High Frequency Mode)
T
T
Feedback Clock Path Delay Variation
T
DUTYCYCRANGE_1
DUTYCYCRANGE_1_50
DUTYCYCRANGE_50_100
DUTYCYCRANGE_100_200
DUTYCYCRANGE_200_400
DUTYCYCRANGE_400
CYCLFDLL
CYCLFFX
CYCHFDLL
CYCHFFX
PERLFDLL
PERLFFX
PERHFDLL
PERHFFX
CLKFB_DELAY_VAR
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
If both DLL and DFS outputs are used, follow the more restrictive specifications.
This duty cycle specification does not apply to the GTP_DUAL to DCM or GTX_DUAL to DCM connection. The GTP transceivers drive the
DCMs at the following frequencies: 320 MHz for -1 speed grade devices, 375 MHz for -2 speed grade devices, or 375 MHz for -3 speed
grade devices. The GTX transceivers drive the DCMs at the following frequencies: 450 MHz for -1 speed grade devices or 500 MHz for -2
speed grade devices.
Symbol
PSCLK only
PSCLK and CLKIN
CLKIN (using DLL outputs)
CLKIN (using DFS outputs)
CLKIN (using DLL outputs)
CLKIN (using DFS outputs)
CLKIN (using DLL outputs)
CLKIN (using DFS outputs)
CLKIN (using DLL outputs)
CLKIN (using DFS outputs)
CLKFB off-chip feedback
www.xilinx.com
Description
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
300.00
300.00
150.00
150.00
Frequency Range
1.00
1.00
1.00
1.00
1.00
200 - 400 MHz
-3
100 - 200 MHz
50 - 100 MHz
1 - 50 MHz
> 400 MHz
< 1 MHz
Speed Grade
300.00
300.00
150.00
150.00
1.00
1.00
1.00
1.00
1.00
-2
(4)
25 - 75
25 - 75
30 - 70
40 - 60
45 - 55
45 - 55
345.00
345.00
173.00
173.00
Value
1.15
1.15
1.15
1.15
1.15
-1
Units
Units
ps
ps
ps
ps
ns
ns
ns
ns
ns
%
%
%
%
%
%
59