XCV405E-6BG560C Xilinx Inc, XCV405E-6BG560C Datasheet - Page 28

• Manufacturer Part Number: XCV405E-6BG560C
• Description: IC FPGA 1.8V C-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV405E-6BG560C

• Number Of Logic Elements/cells: 10800
• Number Of Labs/clbs: 2400
• Total Ram Bits: 573440
• Number Of I /o: 404
• Number Of Gates: 129600
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Board-level de-skew is not required for low-fanout clock net-
works. It is recommended for systems that have fanout lim-
itations on the clock network, or if the clock distribution chip
cannot handle the load.
Do not use the DLL output clock signals until after activation
of the LOCKED signal. Prior to the activation of the
LOCKED signal, the DLL output clocks are not valid and
can exhibit glitches, spikes, or other spurious movement.
The dll_mirror_1 files in the xapp132.zip file show the VHDL
and Verilog implementation of this circuit.
De-Skew of Clock and Its 2x Multiple
The circuit shown in
plier and also uses the CLK0 clock output with zero ns skew
between registers on the same chip. A clock divider circuit
could alternatively be implemented using similar connec-
tions.
Module 2 of 4
24
Figure 29: DLL De-skew of Clock and 2x Multiple
Figure 28: DLL De-skew of Board Level Clock
Other Non_Virtex-E Chips
Virtex-E Device
IBUFG
IBUF
IBUFG
IBUFG
Non-Virtex-E Chip
Non-Virtex-E Chip
Figure 29
CLKIN
CLKFB
RST
CLKIN
CLKFB
RST
CLKIN
CLKFB
RST
CLKDLL
CLKDLL
CLKDLL
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
LOCKED
implements a 2x clock multi-
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
LOCKED
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
LOCKED
ds022_029_121099
BUFG
OBUF
BUFG
OBUF
BUFG
ds022_030_121099
www.xilinx.com
1-800-255-7778
Because any single DLL can access only two BUFGs at
most, any additional output clock signals must be routed
from the DLL in this example on the high speed backbone
routing.
The dll_2x files in the xapp132.zip file show the VHDL and
Verilog implementation of this circuit.
Virtex-E 4x Clock
Two DLLs located in the same half-edge (top-left, top-right,
bottom-right, bottom-left) can be connected together, with-
out using a BUFG between the CLKDLLs, to generate a 4x
clock as shown in
devices, have four clock networks that are available for inter-
nal de-skewing of the clock. Each of the eight DLLs have
access to two of the four clock networks. Although all the
DLLs can be used for internal de-skewing, the presence of
two GCLKBUFs on the top and two on the bottom indicate
that only two of the four DLLs on the top (and two of the four
DLLs on the bottom) can be used for this purpose.
The dll_4xe files in the xapp 32.zip file show the DLL imple-
mentation in Verilog for Virtex-E devices. These files can be
found at:
ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip
Using Block SelectRAM+ Features
The Virtex FPGA Series provides dedicated blocks of
on-chip, true dual-read/write port synchronous RAM, with
4096 memory cells. Each port of the block SelectRAM+
memory can be independently configured as a read/write
port, a read port, a write port, and can be configured to a
specific data width. block SelectRAM+ memory offers new
capabilities, allowing FPGA designers to simplify designs.
Figure 30: DLL Generation of 4x Clock in Virtex-E
IBUFG
Figure
RST
RST
CLKIN
CLKFB
CLKIN
CLKFB
CLKDLL-S
CLKDLL-P
30. Virtex-E devices, like the Virtex
Devices
DS025-2 (v2.3) November 19, 2002
LOCKED
LOCKED
CLK180
CLK270
CLK180
CLK270
CLKDV
CLKDV
CLK2X
CLK2X
CLK90
CLK90
CLK0
CLK0
BUFG
OBUF
ds022_031_041901
INV
R