XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 212

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Chapter 5: Configurable Logic Blocks (CLBs)
212
Port Signals
X-Ref Target - Figure 5-32
Instantiating several distributed RAM primitives can be used to implement wide memory
blocks.
Each distributed RAM port operates independently of the other while reading the same set
of memory cells.
Clock – WCLK
The clock is used for the synchronous write. The data and the address input pins have
setup times referenced to the WCLK pin.
Enable – WE/WED
The enable pin affects the write functionality of the port. An active write enable prevents
any writing to memory cells. An active write enable causes the clock edge to write the data
input signal to the memory location pointed to by the address inputs.
Address – A[#:0], DPRA[#:0], and ADDRA[#:0] – ADDRD[#:0]
The address inputs A[#:0] (for single-port and dual-port), DPRA[#:0] (for dual-port), and
ADDRA[#:0] – ADDRD[#:0] (for quad-port) select the memory cells for read or write. The
width of the port determines the required address inputs. Some of the address inputs are
not buses in VHDL or Verilog instantiations.
address pins.
Data In – D, DID[#:0]
The data input D (for single-port and dual-port) and DID[#:0] (for quad-port) provide the
new data value to be written into the RAM.
Data Out – O, SPO, DPO and DOA[#:0] – DOD[#:0]
The data out O (single-port or SPO), DPO (dual-port), and DOA[#:0] – DOD[#:0] (quad-
port) reflects the contents of the memory cells referenced by the address inputs. Following
an active write clock edge, the data out (O, SPO, or DOD[#:0]) reflects the newly written
data.
WCLK
A[#:0]
WE
Figure 5-32: Single-Port, Dual-Port, and Quad-Port Distributed RAM Primitives
D
RAM#X1S
DPRA[#:0]
O
WCLK
www.xilinx.com
A[#:0]
WE
D
RAM#X1D
Read Port
R/W Port
Table 5-11
SPO
DPO
ADDRD[#:0]
ADDRC[#:0]
ADDRB[#:0]
ADDRA[#:0]
DI[A:D][#:0]
summarizes the function of each
WCLK
WE
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Read Port
Read Port
Read Port
RAM#M
R/W Port
UG190_5_32_112108
DOD[#:0]
DOC[#:0]
DOB[#:0]
DOA[#:0]