XC2V1500-5FGG676I Xilinx Inc, XC2V1500-5FGG676I Datasheet - Page 88
![IC FPGA VIRTEX-II 1.5M 676-FBGA](/photos/6/73/67300/b-676_sml.jpg)
XC2V1500-5FGG676I
Manufacturer Part Number
XC2V1500-5FGG676I
Description
IC FPGA VIRTEX-II 1.5M 676-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-IIr
Datasheet
1.XC2V250-4FGG256C.pdf
(318 pages)
Specifications of XC2V1500-5FGG676I
Number Of Labs/clbs
1920
Total Ram Bits
884736
Number Of I /o
392
Number Of Gates
1500000
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Available stocks
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Manufacturer
Quantity
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Company:
Part Number:
XC2V1500-5FGG676I
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Table 47: Sample Window
Table 48: Pin-to-Pin Setup/Hold: Source-Synchronous Configuration
DS031-3 (v3.5) November 5, 2007
Product Specification
Notes:
1. This parameter indicates the total sampling error of Virtex-II DDR input registers across voltage, temperature, and process. The
Notes:
1. IFF = Input Flip-Flop
2. The timing values were measured using the fine-phase adjustment feature of the DCM.
3. The worst-case duty-cycle distortion and DCM jitter on CLK0 and CLK180 is included in these measurements.
Sampling Error at Receiver Pins
Data Input Set-Up and Hold Times Relative to a Forwarded
Clock Input Pin, Using DCM and Global Clock Buffer.
For situations where clock and data inputs conform to
different standards, adjust the setup and hold values
accordingly using the values shown in
Characteristics Standard Adjustments, page
No Delay
Global Clock and IFF with DCM
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 and CLK180 DCM jitter
- Worst-case Duty-Cycle Distortion - T
- DCM accuracy (phase offset)
- DCM phase shift resolution.
These measurements do not include package or clock tree skew.
Description
R
Description
(1)
IOB Input Switching
DCD_CLK180
11.
Symbol
T
SAMP
www.xilinx.com
Symbol
T
T
PSDCM
Virtex-II Platform FPGAs: DC and Switching Characteristics
PHDCM
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
XC2V250
XC2V500
XC2V40
XC2V80
Device
/
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
XC2V250
XC2V500
XC2V40
XC2V80
Device
500
500
500
500
500
500
500
500
500
500
-6
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
-6
Speed Grade
Speed Grade
500
500
500
500
500
500
500
500
500
500
500
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.6
0.2/0.6
0.2/0.6
-5
-5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.6
0.2/0.6
0.2/0.6
0.2/0.7
550
550
550
550
550
550
550
550
550
550
550
-4
-4
Module 3 of 4
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
40
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