XC5VLX30-3FFG676C Xilinx Inc, XC5VLX30-3FFG676C Datasheet - Page 3
![IC FPGA VIRTEX-5 30K 676FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-3FFG676C
Manufacturer Part Number
XC5VLX30-3FFG676C
Description
IC FPGA VIRTEX-5 30K 676FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-3FFG676C
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
400
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX30-3FFG676C
Manufacturer:
XILINX
Quantity:
188
Company:
Part Number:
XC5VLX30-3FFG676C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Virtex-5 FPGA Logic
•
•
•
•
550 MHz Clock Technology
•
•
•
•
SelectIO Technology
•
•
•
•
•
•
DS100 (v5.0) February 6, 2009
Product Specification
On average, one to two speed grade improvement over
Virtex-4 devices
Cascadable 32-bit variable shift registers or 64-bit
distributed memory capability
Superior routing architecture with enhanced diagonal
routing supports block-to-block connectivity with
minimal hops
Up to 330,000 logic cells including:
−
−
−
−
Up to six Clock Management Tiles (CMTs)
−
−
−
−
−
−
−
−
−
−
Differential clock tree structure for optimized low-jitter
clocking and precise duty cycle
32 global clock networks
Regional, I/O, and local clocks in addition to global
clocks
Up to 1,200 user I/Os
Wide selection of I/O standards from 1.2V to 3.3V
Extremely high-performance
−
−
True differential termination on-chip
Same edge capture at input and output I/Os
Extensive memory interface support
Up to 207,360 internal fabric flip-flops with clock enable
(XC5VLX330)
Up to 207,360 real 6-input look-up tables (LUTs) with
greater than 13 million total LUT bits
Two outputs for dual 5-LUT mode gives enhanced
utilization
Logic expanding multiplexers and I/O registers
Each CMT contains two DCMs and one PLL—up to
eighteen total clock generators
Flexible DCM-to-PLL or PLL-to-DCM cascade
Precision clock deskew and phase shift
Flexible frequency synthesis
Multiple operating modes to ease performance trade-off
decisions
Improved maximum input/output frequency
Fine-grained phase shifting resolution
Input jitter filtering
Low-power operation
Wide phase shift range
Up to 800 Mb/s HSTL and SSTL
(on all single-ended I/Os)
Up to 1.25 Gb/s LVDS (on all differential I/O pairs)
R
www.xilinx.com
550 MHz Integrated Block Memory
•
•
•
•
•
•
•
•
•
•
•
550 MHz DSP48E Slices
•
•
•
•
•
•
•
ChipSync Source-Synchronous
Interfacing Logic
•
•
•
•
•
Up to 16.4 Mbits of integrated block memory
36-Kbit blocks with optional dual 18-Kbit mode
True dual-port RAM cells
Independent port width selection (x1 to x72)
−
−
−
−
Multirate FIFO support logic
−
Synchronous FIFO support without Flag uncertainty
Optional pipeline stages for higher performance
Byte-write capability
Dedicated cascade routing to form 64K x 1 memory
without using FPGA routing
Integrated optional ECC for high-reliability memory
requirements
Special reduced-power design for 18 Kbit (and below)
operation
25 x 18 two’s complement multiplication
Optional pipeline stages for enhanced performance
Optional 48-bit accumulator for multiply accumulate
(MACC) operation with optional accumulator cascade
to 96-bits
Integrated adder for complex-multiply or multiply-add
operation
Optional bitwise logical operation modes
Independent C registers per slice
Fully cascadable in a DSP column without external
routing resources
Works in conjunction with SelectIO technology to
simplify source-synchronous interfaces
Per-bit deskew capability built into all I/O blocks
(variable delay line on all inputs and outputs)
Dedicated I/O and regional clocking resources (pins
and trees)
Built-in data serializer/deserializer logic with
corresponding clock divider support in all I/O
Networking/telecommunication interfaces up to
1.25 Gb/s per I/O
Up to x36 total per port for true dual port operation
Up to x72 total per port for simple dual port operation
(one Read port and one Write port)
Memory bits plus parity/sideband memory support for
x9, x18, x36, and x72 widths
Configurations from 32K x 1 to 512 x 72
(8K x 4 to 512 x 72 for FIFO operation)
Full and Empty flag with fully programmable Almost Full
and Almost Empty flags
Virtex-5 Family Overview
3