XC5VLX30-3FF676C Xilinx Inc, XC5VLX30-3FF676C Datasheet - Page 209
![IC FPGA VIRTEX-5 30K 676FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-3FF676C
Manufacturer Part Number
XC5VLX30-3FF676C
Description
IC FPGA VIRTEX-5 30K 676FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-3FF676C
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
400
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA, FCBGA
For Use With
HW-AFX-FF676-500-G - BOARD DEV VIRTEX 5 FF676
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Clock Event 1: Shift In
During a write (Shift In) operation, the single-bit content of the register at the address on
the A/B/C/D inputs is changed, as data is shifted through the SRL. The data written to
this register is reflected on the A/B/C/D outputs synchronously, if the address is
unchanged during the clock event. If the A/B/C/D inputs are changed during a clock
event, the value of the data at the addressable output (A/B/C/D outputs) is invalid.
•
•
Clock Event 2: Shift In
•
Clock Event 3: Shift In/Addressable (Asynchronous) READ
All Read operations are asynchronous to the CLK signal. If the address is changed
(between clock events), the contents of the register at that address are reflected at the
addressable output (A/B/C/D outputs) after a delay of length T
through a LUT).
•
•
Clock Event 32: MSB (Most Significant Bit) Changes
At time T
in this case) on the DMUX output of the slice via the MC31 output of LUT A (SRL). This is
also applicable to the AMUX, BMUX, CMUX, DMUX, and COUT outputs at time T
T
WOSCO
At time T
enabling the SRL for the Write operation that follows.
At time T
and is reflected on the A/B/C/D output after a delay of length T
1. Since the address 0 is specified at clock event 1, the data on the DI input is reflected
at A/B/C/D output, because it is written to register 0.
At time T
and is reflected on the A/B/C/D output after a delay of length T
2. Since the address 0 is still specified at clock event 2, the data on the DI input is
reflected at the D output, because it is written to register 0.
At time T
and is reflected on the A/B/C/D output T
The address is changed (from 0 to 2). The value stored in register 2 at this time is a 0
(in this example, this was the first data shifted in), and it is reflected on the A/B/C/D
output after a delay of length T
after clock event 1.
REG
WS
DS
DS
DS
after clock event 32, the first bit shifted into the SRL becomes valid (logical 0
before clock event 1 the data becomes valid (0) at the DI input of the SRL
before clock event 2, the data becomes valid (1) at the DI input of the SRL
before clock event 3, the data becomes valid (1) at the DI input of the SRL
before clock event 1, the write-enable signal (WE) becomes valid-High,
www.xilinx.com
ILO
.
REG
time after clock event 3.
CLB / Slice Timing Models
ILO
(propagation delay
REG
REG
after clock event
after clock event
REG
and
209
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