XC5VLX50-2FFG324C Xilinx Inc, XC5VLX50-2FFG324C Datasheet - Page 18
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XC5VLX50-2FFG324C
Manufacturer Part Number
XC5VLX50-2FFG324C
Description
IC FPGA VIRTEX-5 50K 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-2FFG324C
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
1769472
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50-2FFG324C
Manufacturer:
XilinxInc
Quantity:
3 000
Company:
Part Number:
XC5VLX50-2FFG324C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 35: GTP_DUAL Tile Receiver Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
4.
5.
6.
SJ Jitter Tolerance
SJ Jitter Tolerance with Stressed Eye
Using PLL_RXDIVSEL_OUT = 1 only.
Indicates the maximum offset between the receiver reference clock and the serial data. For example, a reference clock with ±100 ppm
resolution results in a maximum offset of 200 ppm between the reference clock and the serial data.
CDR 1st-order step size set to 2.
All jitter values are based on a Bit Error Ratio of 1e
Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.
Stimulus signal includes 0.4UI of DJ and 0.17UI of RJ. RX equalizer is enabled.
R
JT_TJSE
JT_SJSE
R
JT_SJ
JT_SJ
JT_SJ
JT_SJ
JT_SJ
JT_SJ
JT_SJ
JT_SJ
Symbol
XOOBVDPP
F
XPPMTOL
R
R
GTPRX
XSST
XRL
3.75
2.50
2.00
1.00
500
500
100
3.2
3.2
3.2
(4)
Serial data rate
OOB detect threshold
peak-to-peak
Receiver spread-spectrum
tracking
Run length (CID)
Data/REFCLK PPM offset
tolerance
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Total Jitter with Stressed
Eye
Sinusoidal Jitter with
Stressed Eye
(6)
(1)
(2)
(6)
(4)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
–12
Description
.
RX oversampler not enabled
RX oversampler enabled
OOBDETECT_THRESHOLD = 100
Modulated @ 33 KHz
Internal AC capacitor bypassed
CDR 2
PLL_RXDIVSEL_OUT = 1
CDR 2
PLL_RXDIVSEL_OUT = 2
CDR 2
PLL_RXDIVSEL_OUT = 4
CDR 2
3.75 Gb/s
3.20 Gb/s
2.50 Gb/s
2.00 Gb/s
1.00 Gb/s
500 Mb/s
500 Mb/s OS
100 Mb/s OS
3.20 Gb/s
3.20 Gb/s
www.xilinx.com
nd
nd
nd
nd
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
-order loop disabled with
-order loop disabled with
-order loop disabled with
-order loop enabled
(3)
(3)
(3)
–5000
–1000
–200
–200
–100
0.30
0.40
0.40
0.40
0.30
0.30
0.30
0.30
0.87
0.30
Min
0.5
0.1
60
Typ
105
F
GTPMAX
1000
Max
165
150
200
200
100
0.5
0
Units
Gb/s
Gb/s
ppm
ppm
ppm
ppm
ppm
mV
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
18