XC2V1500-4FFG896I Xilinx Inc, XC2V1500-4FFG896I Datasheet - Page 25
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XC2V1500-4FFG896I
Manufacturer Part Number
XC2V1500-4FFG896I
Description
IC FPGA VIRTEX-II 1.5M 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-IIr
Datasheet
1.XC2V250-4FGG256C.pdf
(318 pages)
Specifications of XC2V1500-4FFG896I
Number Of Labs/clbs
1920
Total Ram Bits
884736
Number Of I /o
528
Number Of Gates
1500000
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
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Multiplexers
Virtex-II function generators and associated multiplexers
can implement the following:
•
•
•
•
Fast Lookahead Carry Logic
Dedicated carry logic provides fast arithmetic addition and
subtraction. The Virtex-II CLB has two separate carry
chains, as shown in the
The height of the carry chains is two bits per slice. The carry
chain in the Virtex-II device is running upward. The dedi-
cated carry path and carry multiplexer (MUXCY) can also
DS031-2 (v3.5) November 5, 2007
Product Specification
4:1 multiplexer in one slice
8:1 multiplexer in two slices
16:1 multiplexer in one CLB element (4 slices)
32:1 multiplexer in two CLB elements (8 slices)
R
G
G
F
F
Figure
24.
Figure 23: MUXF5 and MUXFX multiplexers
Slice S3
Slice S2
Slice S1
Slice S0
www.xilinx.com
G
G
F
F
Each Virtex-II slice has one MUXF5 multiplexer and one
MUXFX multiplexer. The MUXFX multiplexer implements
the MUXF6, MUXF7, or MUXF8, as shown in
Each CLB element has two MUXF6 multiplexers, one
MUXF7 multiplexer and one MUXF8 multiplexer. Examples
of multiplexers are shown in the Virtex-II Platform FPGA
User Guide. Any LUT can implement a 2:1 multiplexer.
be used to cascade function generators for implementing
wide logic functions.
Arithmetic Logic
The arithmetic logic includes an XOR gate that allows a
2-bit full adder to be implemented within a slice. In addition,
a dedicated AND (MULT_AND) gate (shown in
improves the efficiency of multiplier implementation.
CLB
Virtex-II Platform FPGAs: Functional Description
MUXF8 combines
the two MUXF7 outputs
(Two CLBs)
MUXF6 combines the two MUXF5
outputs from slices S2 and S3
MUXF7 combines the two MUXF6
outputs from slices S0 and S2
MUXF6 combines the two MUXF5
outputs from slices S0 and S1
DS031_08_100201
Module 2 of 4
Figure
Figure
23.
16)
17
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