XCV300-4FG456I Xilinx Inc, XCV300-4FG456I Datasheet - Page 14

• Manufacturer Part Number: XCV300-4FG456I
• Description: IC FPGA 2.5V I-TEMP 456-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™r

Specifications of XCV300-4FG456I

• Number Of Logic Elements/cells: 6912
• Number Of Labs/clbs: 1536
• Total Ram Bits: 65536
• Number Of I /o: 312
• Number Of Gates: 322970
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 456-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™ 2.5 V Field Programmable Gate Arrays
Table 5: Boundary Scan Instructions
Module 2 of 4
10
SAMPLE/PRELOAD
Boundary-Scan
USERCODE
RESERVED
Command
CFG_OUT
EXTEST
IDCODE
BYPASS
USER 1
USER 2
CFG_IN
JSTART
INTEST
Figure 11: Boundary Scan Bit Sequence
HIGHZ
Bit 0 ( TDO end)
Bit 1
Bit 2
(TDI end)
Right half of Top-edge IOBs (Right-to-Left)
GCLK2
GCLK3
Left half of Top-edge IOBs (Right-to-Left)
Left-edge IOBs (Top-to-Bottom)
M1
M0
M2
Left half of Bottom-edge IOBs (Left-to-Right)
GCLK1
GCLK0
Right half of Bottom-edge IOBs (Left-to-Right)
DONE
PROG
Right-edge IOBs (Bottom -to-Top)
CCLK
Code(4:0)
All other
Binary
00000
00001
00010
00011
00100
00101
00111
01000
01001
01010
01100
11111
codes
Enables boundary-scan
EXTEST operation
Enables boundary-scan
SAMPLE/PRELOAD
operation
Access user-defined
register 1
Access user-defined
register 2
Access the configuration
bus for read operations.
Access the configuration
bus for write operations.
Enables boundary-scan
INTEST operation
Enables shifting out
USER code
Enables shifting out of ID
Code
3-states output pins while
enabling the Bypass
Register
Clock the start-up
sequence when
StartupClk is TCK
Enables BYPASS
Xilinx reserved
instructions
Description
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www.xilinx.com
1-800-255-7778
Identification Registers
The IDCODE register is supported. By using the IDCODE,
the device connected to the JTAG port can be determined.
The IDCODE register has the following binary format:
vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1
where
v = the die version number
f = the family code (03h for Virtex family)
a = the number of CLB rows (ranges from 010h for XCV50
to 040h for XCV1000)
c = the company code (49h for Xilinx)
The USERCODE register is supported. By using the USER-
CODE, a user-programmable identification code can be
loaded and shifted out for examination. The identification
code is embedded in the bitstream during bitstream gener-
ation and is valid only after configuration.
Table 6: IDCODEs Assigned to Virtex FPGAs
Including Boundary Scan in a Design
Since the boundary scan pins are dedicated, no special ele-
ment needs to be added to the design unless an internal
data register (USER1 or USER2) is desired.
If an internal data register is used, insert the boundary scan
symbol and connect the necessary pins as appropriate.
Development System
Virtex FPGAs are supported by the Xilinx Foundation and
Alliance CAE tools. The basic methodology for Virtex design
consists of three interrelated steps: design entry, imple-
mentation, and verification. Industry-standard tools are
used for design entry and simulation (for example, Synop-
sys FPGA Express), while Xilinx provides proprietary archi-
tecture-specific tools for implementation.
The Xilinx development system is integrated under the Xil-
inx Design Manager (XDM™) software, providing designers
XCV1000
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV50
FPGA
DS003-2 (v2.8.1) December 9, 2002
Product Specification
v061C093h
v0610093h
v0614093h
v0618093h
v0620093h
v0628093h
v0630093h
v0638093h
v0640093h
IDCODE
R