XC5VLX30-2FFG324C Xilinx Inc, XC5VLX30-2FFG324C Datasheet - Page 74
![IC FPGA VIRTEX-5 30K 324FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-2FFG324C
Manufacturer Part Number
XC5VLX30-2FFG324C
Description
IC FPGA VIRTEX-5 30K 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-2FFG324C
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
For Use With
HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX30-2FFG324C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 2: Clock Management Technology
74
PLL To and From DCM
DCM To and From PMCD
Figure 2-7
same CMT block. The PLL can drive either DCM in the same CMT block using a dedicated
connection. Similarly, the DCM can drive the PLL within the same CMT block with a
dedicated connection. There is no BUFGCTRL required between the PLL and the DCM.
X-Ref Target - Figure 2-7
The PMCD block is not available in the Virtex-5 devices. However, a limited retargeting
using the PLL is possible. Refer to
for more information.
From any IBUFG implementation
From any BUFG implementation
summarizes the dedicated connection between the DCM and the PLL in the
Figure 2-7: DCM and PLL Connection in Same CMT Block
www.xilinx.com
PLL in Virtex-4 FPGA PMCD Legacy Mode in Chapter 3
PLL to DCM Input
CLKFBIN
PLL to DCM Input
CLKFB
DCM to PLL Input
CLKIN
DCM to PLL Input
CLKFB
CLKIN
CLKIN
DCM2
DCM1
PLL
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Routing (BUFG)
Routing (BUFG)
Routing (BUFG)
To Global
ug190_2_07_072307
To Global
To Global
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