XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 34
Manufacturer Part Number
IC FPGA VIRTEX-II PRO 896-FBGA
Specifications of XC2VP7-5FFG896I
Number Of Logic Elements/cells
Number Of Labs/clbs
Total Ram Bits
Number Of I /o
Voltage - Supply
1.425 V ~ 1.575 V
-40°C ~ 100°C
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
The PPC405 provides an interface to an interrupt controller
that is logically outside the PPC405 core. This controller
combines the asynchronous interrupt inputs and presents
them to the embedded core as a single interrupt signal. The
sources of asynchronous interrupts are external signals, the
JTAG/debug unit, and any implemented peripherals.
All architected resources on the embedded PPC405 core
can be accessed through the debug logic. Upon a debug
event, the PPC405 core provides debug information to an
external debug tool. Three different types of tools are sup-
ported depending on the debug mode: ROM monitors,
JTAG debuggers, and instruction trace tools.
In internal debug mode, a debug event enables excep-
tion-handling software at a dedicated interrupt vector to take
DS083 (v4.7) November 5, 2007
Figure 17: Relationship of Timer Facilities to Base
TBL (32 bits)
Bit 11 (2
Bit 15 (2
Bit 19 (2
Bit 23 (2 clocks)
Time Base (Incrementer)
Bit 11 (2
Bit 15 (2
TBU (32 bits)
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
over the CPU core and communicate with a debug tool. The
debug tool has read-write access to all registers and can set
hardware or software breakpoints. ROM monitors typically
use the internal debug mode.
In external debug mode, the CPU core enters stop state
(stops instruction execution) when a debug event occurs.
This mode offers a debug tool read-write access to all regis-
ters in the PPC405 core. Once the CPU core is in stop state,
the debug tool can start the CPU core, step an instruction,
freeze the timers, or set hardware or software break points.
In addition to CPU core control, the debug logic is capable
of writing instructions into the instruction cache, eliminating
the need for external memory during initial board bring-up.
Communication to a debug tool using external debug mode
is through the JTAG port.
Debug wait mode offers the same functionality as external
debug mode with one exception. In debug wait mode, the
CPU core goes into wait state instead of stop state after a
debug event. Wait state is identical to stop state until an
interrupt occurs. In wait state, the PPC405 core can vector
to an exception handler, service an interrupt and return to
wait state. This mode is particularly useful when debugging
real time control systems.
Real-time trace debug mode is always enabled. The debug
logic continuously broadcasts instruction trace information
to the trace port. When a debug event occurs, the debug
logic signals an external debug tool to save instruction trace
information before and after the event. The number of
instructions traced depends on the trace tool.
Debug events signal the debug logic to stop the CPU core,
put the CPU core in debug wait state, cause a debug excep-
tion or save instruction trace information.
Big Endian and Little Endian Support
The embedded PPC405 core supports big endian or little
endian byte ordering for instructions stored in external
memory. Since the PowerPC architecture is big endian
internally, the ICU rearranges the instructions stored as little
endian into the big endian format. Therefore, the instruction
cache always contains instructions in big endian format so
that the byte ordering is correct for the execution unit. This
feature allows the 405 core to be used in systems designed
to function in a little endian environment.
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