XC5VLX30-1FF676C Xilinx Inc, XC5VLX30-1FF676C Datasheet - Page 98

• Manufacturer Part Number: XC5VLX30-1FF676C
• Description: IC FPGA VIRTEX-5 30K 676FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX30-1FF676C

• Number Of Logic Elements/cells: 30720
• Number Of Labs/clbs: 2400
• Total Ram Bits: 1179648
• Number Of I /o: 400
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA, FCBGA
• Package: 676FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 30720
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 400
• Ram Bits: 1179648
• For Use With: HW-AFX-FF676-500-G - BOARD DEV VIRTEX 5 FF676
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 3: Phase-Locked Loops (PLLs)
Table 3-4: PLL Attributes
98
COMPENSATION
BANDWIDTH
CLKOUT[0:5]_DIVIDE
CLKOUT[0:5]_PHASE
CLKOUT[0:5]_
DUTY_CYCLE
CLKFBOUT_MULT
Attribute
PLL Attributes
Integer
Integer
String
String
Type
Real
Real
SOURCE_SYNCHRONOUS
SYSTEM_SYNCHRONOUS
Allowed Values
–360.0 to 360.0
OPTIMIZED
0.01 to 0.99
1 to 128
1 to 64
HIGH
LOW
www.xilinx.com
SYNCHRONOUS
OPTIMIZED
SYSTEM_
Default
0.50
0.0
1
1
Specifies the PLL phase
compensation for the incoming
clock. SYSTEM_SYNCHRONOUS
attempts to compensate all clock
delay for 0 hold time.
SOURCE_SYNCHRONOUS is
used when a clock is provided
with data and thus phased with
the clock.
Additional attributes
automatically selected by the ISE
software:
INTERNAL
EXTERNAL
DCM2PLL
PLL2DCM
Specifies the PLL programming
algorithm affecting the jitter, phase
margin and other characteristics of
the PLL.
Specifies the amount to divide the
associated CLKOUT clock output
if a different frequency is desired.
This number in combination with
the CLKFBOUT_MULT and
DIVCLK_DIVIDE values will
determine the output frequency.
Allows specification of the output
phase relationship of the
associated CLKOUT clock output
in number of degrees offset (i.e., 90
indicates a 90° or ¼ cycle offset
phase offset while 180 indicates a
180° offset or ½ cycle phase offset).
Specifies the Duty Cycle of the
associated CLKOUT clock output
in percentage (i.e., 0.50 will
generate a 50% duty cycle).
Specifies the amount to multiply
all CLKOUT clock outputs if a
different frequency is desired. This
number, in combination with the
associated CLKOUT#_DIVIDE
value and DIVCLK_DIVIDE
value, will determine the output
frequency.
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Description