XC5VLX20T-1FFG323C Xilinx Inc, XC5VLX20T-1FFG323C Datasheet - Page 9

• Manufacturer Part Number: XC5VLX20T-1FFG323C
• Description: IC FPGA VIRTEX-5LX 20K 323-FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX20T-1FFG323C

• Total Ram Bits: 958464
• Number Of Logic Elements/cells: 19968
• Number Of Labs/clbs: 1560
• Number Of I /o: 172
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 323-BBGA, FCBGA
• No. Of Logic Blocks: 3120
• No. Of Gates: 20000
• No. Of Macrocells: 3120
• No. Of Speed Grades: 1
• No. Of I/o's: 172
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

LVPECL DC Specifications (LVPECL_25)
These values are valid when driving a 100Ω differential load only, i.e., a 100Ω resistor between the two receiver pins. The
V
ranges.
Virtex-5 FPGA User Guide, Chapter 6, SelectIO Resources.
Table 11: LVPECL DC Specifications
PowerPC 440 Switching Characteristics
Consult the Embedded Processor Block in Virtex-5 FPGAs Reference Guide for further information.
Table 12: Processor Block Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
Notes:
1.
2.
V
V
V
V
CPMC440CLK
CPMINTERCONNECTCLK
CPMPPCS0PLBCLK
CPMPPCS1PLBCLK
CPMPPCMPLBCLK
CPMMCCLK
CPMFCMCLK
CPMDCRCLK
CPMDMA0LLCLK
CPMDMA1LLCLK
CPMDMA2LLCLK
CPMDMA3LLCLK
JTGC440TCK
CPMC440TIMERCLOCK
OH
OH
OL
ICM
IDIFF
Symbol
Recommended input maximum voltage not to exceed V
Recommended input minimum voltage not to go below –0.5V.
Typical bus frequencies are provided for reference only, actual frequencies are user-design dependent.
Refer to
levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode
Table 11
Clock Name
DS567
Output High Voltage
Output Low Voltage
Input Common-Mode Voltage
Differential Input Voltage
summarizes the DC output specifications of LVPECL. For more information on using LVPECL
for maximum clock speed of designs using the DDR2 Memory Controller for PowerPC® 440 Processors.
DC Parameter
CPU clock
Xbar clock
Slave 0 PLB clock
Slave 1 PLB clock
Master PLB clock
Memory interface clock
FCM clock
FPGA logic DCR clock
DMA0 LL clock
DMA1 LL clock
DMA2 LL clock
DMA3 LL clock
JTAG clock
Timer clock
(1,2)
(1)
(1)
(1)
(1)
(1)
(1)
CCO
(1)
(1)
Description
www.xilinx.com
+ 0.2V.
(1)
(1)(2)
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
V
V
CC
CC
0.100
Min
0.6
– 1.025
– 1.81
366.6
183.3
183.3
183.3
366.6
183.3
1.545
0.795
275
550
275
250
250
250
250
Typ
50
-3
Speed Grade
316.6
158.3
158.3
158.3
316.6
237.5
158.3
237.5
475
250
250
250
250
50
-2
V
V
CC
CC
Max
2.2
1.5
– 0.88
– 1.62
266.6
133.3
133.3
133.3
266.6
133.3
400
200
200
200
200
200
200
50
-1
,
see UG190:
Units
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
V
V
V
V
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