XCV200E-7BG352C Xilinx Inc, XCV200E-7BG352C Datasheet - Page 90
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XCV200E-7BG352C
Manufacturer Part Number
XCV200E-7BG352C
Description
IC FPGA 1.8V C-TEMP 352-MBGA
Manufacturer
Xilinx Inc
Series
Virtex™-Er
Datasheet
1.XCV200E-6CS144C.pdf
(233 pages)
Specifications of XCV200E-7BG352C
Number Of Logic Elements/cells
5292
Number Of Labs/clbs
1176
Total Ram Bits
114688
Number Of I /o
260
Number Of Gates
306393
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
352-LBGA, Metal
Case
BGA
Dc
01+
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
XCV200E-7BG352C
Manufacturer:
NVIDIA
Quantity:
19
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Virtex™-E 1.8 V Field Programmable Gate Arrays
CS144 Chip-Scale Package
XCV50E, XCV100E, XCV200E, XCV300E and XCV400E
devices in CS144 Chip-scale packages have footprint com-
patibility. In the CS144 package, bank pairs that share a
side are internally interconnected, permitting four choices
for V
Table 3: I/O Bank Pairs and Shared Vcco Pins
Pins labeled I0_VREF can be used as either in all parts
unless device-dependent, as indicated in the footnotes. If
the pin is not used as V
Immediately following
Pair information.
Table 4: CS144 — XCV50E, XCV100E, XCV200E
Module 4 of 4
4
Bank
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
CCO
Paired Banks
. See
Banks 0 & 1
Banks 2 & 3
Banks 4 & 5
Banks 6 & 7
Table
IO_WRITE_L5N_YY
IO_LVDS_DLL_L2N
IO_LVDS_DLL_L2P
IO_VREF_L0N_YY
IO_VREF_L4P_YY
3.
Pin Description
IO_CS_L5P_YY
Table
IO_L0P_YY
IO_L1N_YY
IO_L1P_YY
IO_L3N_YY
IO_L3P_YY
IO_L4N_YY
REF
IO_VREF
IO_VREF
IO_VREF
GCK3
GCK2
, it can be used as general I/O.
IO
IO
4, see
Shared V
B12, G11, M13
Table 5
N1, N7, N13
A2, A13, D7
B2, G2, M2
CCO
is Differential
Pins
Pin #
D9
C10
D10
B4
A3
A6
B3
A4
A5
C6
C4
D6
A7
A8
C8
D8
C9
B5
B7
www.xilinx.com
1-800-255-7778
2
1
2
Table 4: CS144 — XCV50E, XCV100E, XCV200E
Bank
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
IO_DOUT_BUSY_L6P_YY
IO_DIN_D0_L6N_YY
IO_INIT_L14N_YY
IO_D5_L12N_YY
IO_D7_L14P_YY
Pin Description
IO_VREF_L11N
IO_VREF_L13N
IO_D2_L8P_YY
IO_VREF_L7P
IO_VREF_L9P
IO_D4_L11P
IO_L12P_YY
IO_D6_L13P
IO_D1_L7N
IO_L8N_YY
IO_D3_L9N
IO_VREF
IO_VREF
IO_VREF
IO_VREF
IO_VREF
IO_VREF
IO_VREF
IO_L10N
IO_L10P
GCK0
Production Product Specification
IO
IO
IO
IO
IO
IO
DS022-4 (v2.5) March 14, 2003
Pin #
B10
D13
C13
K11
J10
G13
M10
A10
D12
C11
C12
E10
E13
E12
F10
D11
H13
K13
H11
H12
H10
K10
K12
F12
F11
F13
J13
J11
L13
M8
B8
K7
2
1
1
2
1
R
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