XC3S1500-5FGG676C Xilinx Inc, XC3S1500-5FGG676C Datasheet - Page 159
![SPARTAN-3A FPGA 1.5M 676-FBGA](/photos/6/73/67300/b-676_sml.jpg)
XC3S1500-5FGG676C
Manufacturer Part Number
XC3S1500-5FGG676C
Description
SPARTAN-3A FPGA 1.5M 676-FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S1500-5FGG676C
Number Of Logic Elements/cells
29952
Number Of Labs/clbs
3328
Total Ram Bits
589824
Number Of I /o
487
Number Of Gates
1500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA
Package
676FBGA
Family Name
Spartan®-3
Device Logic Units
29952
Device System Gates
1500000
Maximum Internal Frequency
725 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
487
Ram Bits
589824
For Use With
NANO-SPARTAN - KIT NANOBOARD AND SPARTAN3 DC807-1001 - DAUGHTER CARD XILINX SPARTAN 3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S1500-5FGG676C
Manufacturer:
XilinxInc
Quantity:
3 000
Company:
Part Number:
XC3S1500-5FGG676C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S1500-5FGG676C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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User I/Os by Bank
Table 100
tributed between the eight I/O banks for the XC3S400 in the
FG456 package. Similarly,
Table 100: User I/Os Per Bank for XC3S400 in FG456 Package
Table 101: User I/Os Per Bank for XC3S1000, XC3S1500, and XC3S2000 in FG456 Package
DS099-4 (v2.5) December 4, 2009
Product Specification
Bottom
Bottom
Edge
Edge
Right
Right
Left
Left
Top
Top
indicates how the available user-I/O pins are dis-
R
I/O Bank
Bank
I/O
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Table 101
Maximum
Maximum
I/O
I/O
35
35
31
31
35
35
31
31
40
40
43
43
41
40
43
43
shows how the avail-
I/O
I/O
27
27
25
25
21
21
25
25
31
31
37
37
26
25
37
37
www.xilinx.com
able user-I/O pins are distributed between the eight I/O
banks for the XC3S1000, XC3S1500, and XC3S2000 in the
FG456 package.
DUAL
DUAL
0
0
0
0
6
6
0
0
0
0
0
0
6
6
0
0
All Possible I/O Pins by Type
All Possible I/O Pins by Type
Spartan-3 FPGA Family: Pinout Descriptions
DCI
DCI
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
VREF
VREF
4
4
4
4
4
4
4
4
5
5
4
4
5
5
4
4
GCLK
GCLK
2
2
0
0
2
2
0
0
2
2
0
0
2
2
0
0
159
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