XCV50-6TQ144C Xilinx Inc, XCV50-6TQ144C Datasheet - Page 46
![IC FPGA 2.5V C-TEMP 144-TQFP](/photos/6/70/67094/144tqfp_sml.jpg)
XCV50-6TQ144C
Manufacturer Part Number
XCV50-6TQ144C
Description
IC FPGA 2.5V C-TEMP 144-TQFP
Manufacturer
Xilinx Inc
Series
Virtex™r
Datasheet
1.XCV100-5PQ240C.pdf
(76 pages)
Specifications of XCV50-6TQ144C
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
384
Total Ram Bits
32768
Number Of I /o
98
Number Of Gates
57906
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP
Case
TQFP144
Dc
03+
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XCV50-6TQ144C
Manufacturer:
XIL
Quantity:
1 238
Company:
Part Number:
XCV50-6TQ144C
Manufacturer:
XILINX
Quantity:
988
Virtex™ 2.5 V Field Programmable Gate Arrays
Revision History
Module 3 of 4
22
11/98
01/99
02/99
05/99
05/99
07/99
09/99
01/00
Date
Output Jitter: the difference between an ideal
reference clock edge and the actual design.
Period Tolerance: the allowed input clock period change in nanoseconds.
Ideal Period
Actual Period
Version
1.0
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Initial Xilinx release.
Updated package drawings and specs.
Update of package drawings, updated specifications.
Addition of package drawings and specifications.
Replaced FG 676 & FG680 package drawings.
Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit
Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O
Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and
new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and
Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19.
Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated
IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate.
Added IOB Input Switching Characteristics Standard Adjustments.
Speed grade update to preliminary status, Power-on specification and Clock-to-Out
Minimums additions, "0" hold time listing explanation, quiescent current listing update, and
Figure 6 ADDRA input label correction. Added T
Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479,
117153, 117154, and 117612. Modified notes for Recommended Operating Conditions
(voltage and temperature). Changed Bank information for V
T CLKIN
Figure 1: Frequency Tolerance and Clock Jitter
www.xilinx.com
1-800-255-7778
Phase Offset and Maximum Phase Difference
Revision
+/- Jitter
+ Maximum
+ Phase Offset
Phase Difference
IJITCC
parameter, changed T
T CLKIN + T IPTOL
DS003-3 (v3.2) September 10, 2002
CCO
Production Product Specification
ds003_20c_110399
_
in CS144 package on p.43.
OJIT
to T
OPHASE
.
R