XC3S4000-4FGG676C Xilinx Inc, XC3S4000-4FGG676C Datasheet - Page 57
![SPARTAN-3A FPGA 4M STD 676-FBGA](/photos/6/73/67300/b-676_sml.jpg)
XC3S4000-4FGG676C
Manufacturer Part Number
XC3S4000-4FGG676C
Description
SPARTAN-3A FPGA 4M STD 676-FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S4000-4FGG676C
Number Of Logic Elements/cells
62208
Number Of Labs/clbs
6912
Total Ram Bits
1769472
Number Of I /o
489
Number Of Gates
4000000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA
Package
676FBGA
Family Name
Spartan®-3
Device Logic Units
62208
Device System Gates
4000000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
489
Ram Bits
1769472
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S4000-4FGG676C
Manufacturer:
XILINX
Quantity:
80
Company:
Part Number:
XC3S4000-4FGG676C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S4000-4FGG676C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Table 29: Power Voltage Ramp Time Requirements
Table 30: Power Voltage Levels Necessary for Preserving RAM Contents
DS099-3 (v2.5) December 4, 2009
Product Specification
98
Notes:
1.
2.
3.
4.
5.
Notes:
1.
2.
3.
Symbol
T
Symbol
V
V
T
If a limit exists, this specification is based on characterization.
The ramp time is measured from 10% to 90% of the full nominal voltage swing for all I/O standards.
For information on power-on current needs, see
For mask revisions earlier than revision E (see
and XC3S400 devices in QFP packages, and limited to 0.6 ms for the XC3S200, XC3S400, XC3S1500, and XC3S4000 devices in
the FT and FG packages.
For earlier device versions with the FQ fabrication/process code (see
500 µs.
RAM contents include data stored in CMOS configuration latches.
The level of the V
If a brown-out condition occurs where V
the minimum power-on reset voltage indicated in
CCINT
DRAUX
DRINT
CCO
R
V
V
in three-rail power-on sequence
V
V
CCO
CCINT
CCINT
CCAUX
CCO
ramp time for all eight banks
ramp time, only if V
level required to retain RAM data
level required to retain RAM data
supply has no effect on data retention.
Description
CCAUX
CCINT
Spartan-3 FPGA Family: DC and Switching Characteristics
or V
Mask and Fab Revisions, page
is last
Power-On Behavior, page 52
Table 28
CCINT
Description
www.xilinx.com
drops below the retention voltage, then V
All
All
in order to clear out the device configuration content.
Device
Mask and Fab Revisions, page
All
All
Package
55), T
CCO
No limit
No limit
min is limited to 2.0 ms for the XC3S200
Min
(4)
CCAUX
55), T
No limit
or V
Max
CCINT
CCINT
-
Min
2.0
1.0
(5)
must drop below
max is limited to
Units
Units
V
V
57