XC3S1600E-5FGG320C Xilinx Inc, XC3S1600E-5FGG320C Datasheet - Page 113
![IC FPGA SPARTAN-3E 1600K 320FBGA](/photos/6/72/67295/pk071-320_sml.jpg)
XC3S1600E-5FGG320C
Manufacturer Part Number
XC3S1600E-5FGG320C
Description
IC FPGA SPARTAN-3E 1600K 320FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1600E-5FGG320C
Number Of Logic Elements/cells
33192
Number Of Labs/clbs
3688
Total Ram Bits
663552
Number Of I /o
250
Number Of Gates
1600000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
320-BGA
For Use With
HW-XA3S1600E-UNI-G - KIT DEVELOPMENT AUTOMOTIVE ECU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S1600E-5FGG320C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S1600E-5FGG320C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Company:
Part Number:
XC3S1600E-5FGG320C/4I
Manufacturer:
XILINX
Quantity:
150
Production Stepping
The Spartan-3E FPGA family uses production stepping to
indicate improved capabilities or enhanced features.
Stepping 1 is, by definition, a functional superset of Step-
ping 0. Furthermore, configuration bitstreams generated for
Stepping 0 are compatible with Stepping 1.
Designs operating on the Stepping 0 devices perform simi-
larly on a Stepping 1 device.
Table 71: Differences between Spartan-3E Production Stepping Levels
Ordering a Later Stepping
-5C and -4I devices, and -4C devices (with date codes 0901
(2009) and later) always support the Stepping 1 feature set
independent of the stepping code. Optionally, to order only
Stepping 1 for the -4C devices, append an “S1” suffix to the
standard ordering code, where ‘1’ is the stepping number,
as indicated in
DS312-2 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
Production status
Speed grade and operating conditions
JTAG ID code
DCM DLL maximum input frequency
DCM DFS output frequency range(s)
Supports multi-FPGA daisy-chain configurations
from SPI Flash
JTAG configuration supported when FPGA in
BPI mode with a valid image in the attached
parallel NOR Flash PROM
JTAG EXTEST, INTEST, SAMPLE support
Power sequencing when using HSWAP Pull-Up
PCI compliance
Workarounds exist. See
JTAG BYPASS and JTAG configuration are supported
R
Table
72.
Stepping 0 Limitations when Reprogramming via JTAG if FPGA Set for BPI
Yes: XC3S100E, XC3S250E, XC3S500E
www.xilinx.com
No
Requires V
Split ranges at 5 – 90 MHz and
Production from 2005 to 2007
(single range 5 – 307 MHz for
(200 MHz for XC3S1200E)
(2)
: XC3S1200E, XC3S1600E
No, single FPGA only
Differences Between Steppings
Table 71
ences between Stepping 0 devices and Stepping 1 devices.
Table 72: Spartan-3E Optional Stepping Ordering
220 – 307 MHz
Stepping
Number
XC3S1200E)
Stepping 0
CCINT
Different revision fields. See
-4C only
90 MHz
0
1
No
No
(1)
summarizes the feature and performance differ-
before V
Suffix Code
None
CCAUX
S1
Configuration.
240 MHz (–4 speed grade)
275 MHz (–5 speed grade)
Table
Functional Description
Production starting
Continuous range:
5 – 311 MHz (–4)
5 – 333 MHz (–5)
Any sequence
Production
Production
-4C, -4I, -5C
67.
March 2006
Stepping 1
All Devices
Status
Yes
Yes
Yes
Yes
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