XCS40-3PQ240C Xilinx Inc, XCS40-3PQ240C Datasheet - Page 4

• Manufacturer Part Number: XCS40-3PQ240C
• Description: IC FPGA 5V C-TEMP 240-PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™r

Specifications of XCS40-3PQ240C

• Number Of Logic Elements/cells: 1862
• Number Of Labs/clbs: 784
• Total Ram Bits: 25088
• Number Of I /o: 192
• Number Of Gates: 40000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 240-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Spartan and Spartan-XL FPGA Families Data Sheet
A CLB can implement any of the following functions:
•
•
•
•
Implementing wide functions in a single block reduces both
the number of blocks required and the delay in the signal
path, achieving both increased capacity and speed.
The versatility of the CLB function generators significantly
improves system speed. In addition, the design-software
tools can deal with each function generator independently.
This flexibility improves cell usage.
4
Any function of up to four variables, plus any second
function of up to four unrelated variables, plus any third
function of up to three unrelated variables
Note: When three separate functions are generated, one of
the function outputs must be captured in a flip-flop internal to
the CLB. Only two unregistered function generator outputs
are available from the CLB.
Any single function of five variables
Any function of four variables together with some
functions of six variables
Some functions of up to nine variables.
DIN
SR
EC
G4
G3
G2
G1
H1
F4
F3
F2
F1
K
Figure 2: Spartan/XL Simplified CLB Logic Diagram (some features not shown)
G4
G3
G2
G1
F4
F3
F2
F1
G-LUT
F-LUT
Function
Function
G1-G4
F1-F4
Logic
Logic
of
of
G
G
Multiplexer Controlled
by Configuration Program
A
G
H1
F
www.xilinx.com
H-LUT
Function
F-G-H1
Logic
of
B
H
Flip-Flops
Each CLB contains two flip-flops that can be used to regis-
ter (store) the function generator outputs. The flip-flops and
function generators can also be used independently (see
Figure
to either of the two flip-flops. H1 can also drive either
flip-flop via the H-LUT with a slight additional delay.
The two flip-flops have common clock (CK), clock enable
(EC) and set/reset (SR) inputs. Internally both flip-flops are
also controlled by a global initialization signal (GSR) which
is described in detail in
page
Latches (Spartan-XL Family Only)
The Spartan-XL family CLB storage elements can also be
configured as latches. The two latches have common clock
(K) and clock enable (EC) inputs. Functionality of the stor-
age element is described in
20.
2). The CLB input DIN can be used as a direct input
Global Signals: GSR and GTS,
D
CK
EC
D
CK
EC
Table
SR
SR
DS060_02_0506 01
Q
Q
DS060 (v1.8) June 26, 2008
2.
Product Specification
YQ
Y
XQ
X
R