XCV50E-6PQ240I Xilinx Inc, XCV50E-6PQ240I Datasheet - Page 128

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XCV50E-6PQ240I

Manufacturer Part Number
XCV50E-6PQ240I
Description
IC FPGA 1.8V I-TEMP 240-PQFP
Manufacturer
Xilinx Inc
Series
Virtex™-Er
Datasheet

Specifications of XCV50E-6PQ240I

Number Of Logic Elements/cells
1728
Number Of Labs/clbs
384
Total Ram Bits
65536
Number Of I /o
158
Number Of Gates
71693
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
240-BFQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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0
Virtex™-E 1.8 V Field Programmable Gate Arrays
BG560 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A √
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
Module 4 of 4
42
Pair
10
11
12
13
14
15
0
1
2
3
0
1
2
3
4
5
6
7
8
9
Total Outputs: 183, Asynchronous Outputs: 87
Bank
4
5
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Global Differential Clock
AL17
AJ17
D17
D29
C29
D27
C27
C26
D24
C23
D22
C21
A17
A31
B29
A28
B26
A25
B24
B22
Pin
P
IO LVDS
AM17
AM18
E17
C18
E28
D28
E27
B30
E26
D26
E25
D25
E24
C25
E23
D23
E22
A23
E21
D21
Pin
N
AO
NA
NA
NA
NA
8
3
9
7
7
2
8
3
IO_DLL_L15P
IO_DLL_L15N
IO_DLL_L21P
IO_DLL_L21N
Functions
Other
VREF
VREF
VREF
VREF
VREF
VREF
VREF
-
-
-
-
-
-
-
-
-
www.xilinx.com
1-800-255-7778
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
Pair
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Bank
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
C20
C19
D18
D16
C16
C15
D14
D13
D12
C11
D11
D10
E20
E19
E17
B17
E15
E14
E13
Pin
A9
B8
C8
A6
D8
B5
D7
B4
E7
A2
D4
F5
P
Production Product Specification
B21
D20
B20
D19
A19
C18
C17
B16
E16
A15
D15
C14
A13
C13
C12
A11
B11
B10
C10
E10
Pin
C9
C7
C6
C5
D6
A8
B7
A5
A4
E4
B3
N
DS022-4 (v2.5) March 14, 2003
AO
NA
10
11
12
17
9
7
7
2
7
7
9
3
8
7
7
5
IO_LVDS_DLL
Functions
DIN, D0
Other
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
CS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R

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