XC3SD1800A-4FGG676C Xilinx Inc, XC3SD1800A-4FGG676C Datasheet - Page 55
XC3SD1800A-4FGG676C
Manufacturer Part Number
XC3SD1800A-4FGG676C
Description
SPARTAN-3ADSP FPGA 1800K 676FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3A DSPr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3SD3400A-4FGG676C.pdf
(4 pages)
3.XC3SD3400A-4FGG676C.pdf
(101 pages)
Specifications of XC3SD1800A-4FGG676C
Total Ram Bits
1548288
Number Of Logic Elements/cells
37440
Number Of Labs/clbs
4160
Number Of I /o
519
Number Of Gates
1800000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA
No. Of Logic Blocks
4224
No. Of Gates
1800000
No. Of Macrocells
37440
Family Type
Spartan-3A
No. Of Speed Grades
4
No. Of I/o's
519
Clock
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1574 - KIT DEVELOPMENT SPARTAN 3ADSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1538
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Slave Parallel Mode Timing
X-Ref Target - Figure 12
Table 51: Timing for the Slave Parallel Configuration Mode
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
2.
Notes:
1.
2.
(Open-Drain)
Setup Times
T
T
T
Hold Times
T
T
T
Clock Timing
T
T
F
SMDCC
SMCSCC
SMCCW
SMCCD
SMCCCS
SMWCC
CCH
CCL
CCPAR
RDWR_B
PROG_B
Symbol
The numbers in this table are based on the operating conditions set forth in
Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.
It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0–D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0–D7 bus.
To pause configuration, pause CCLK instead of de-asserting CSI_B. See
Loading” for more details.
D0 - D7
(Inputs)
INIT_B
(Input)
CSI_B
(Input)
(Input)
(Input)
CCLK
(2)
The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin
Setup time on the CSI_B pin before the rising transition at the CCLK pin
Setup time on the RDWR_B pin before the rising transition at the CCLK pin
The time from the rising transition at the CCLK pin to the point when data is last held at
the D0-D7 pins
The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the CSO_B pin
The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the RDWR_B pin
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
Frequency of the clock signal at the CCLK input pin No bitstream compression
Figure 12: Waveforms for Slave Parallel Configuration
T
SMCCW
T
SMDCC
Description
Byte 0
T
SMCSCC
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
T
SMCCD
Byte 1
With bitstream compression
UG332,
Table
7.
Chapter 7, section “Non-Continuous SelectMAP Data
T
T
SCCH
MCCH
1/F
CCPAR
All Speed Grades
Byte n
Min
17
7
7
1
0
0
5
5
0
0
T
T
T
MCCL
SCCL
SMCCCS
Byte n+1
Max
80
80
–
–
–
–
–
–
–
–
DS529-3_02_051607
T
SMWCC
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
55