XC3SD1800A-4CSG484C Xilinx Inc, XC3SD1800A-4CSG484C Datasheet - Page 10

• Manufacturer Part Number: XC3SD1800A-4CSG484C
• Description: SPARTAN-3ADSP FPGA 1800K 484CSA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD1800A-4CSG484C

• Total Ram Bits: 1548288
• Number Of Logic Elements/cells: 37440
• Number Of Labs/clbs: 4160
• Number Of I /o: 309
• Number Of Gates: 1800000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA, CSPBGA
• No. Of Logic Blocks: 37440
• No. Of Gates: 1800000
• No. Of Macrocells: 37440
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• No. Of I/o's: 309
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1574 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1537

Power Supply Specifications
Table 4: Supply Voltage Thresholds for Power-On Reset
Table 5: Supply Voltage Ramp Rate
Table 6: Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM Data
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
2.
Notes:
1.
2.
V
Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source.
Apply V
information).
To ensure successful power-on, V
no dips at any point.
V
Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source.
Apply V
information).
To ensure successful power-on, V
no dips at any point.
Symbol
V
V
CCINT
CCINT
DRAUX
V
DRINT
V
Symbol
Symbol
V
V
V
V
CCAUXT
CCAUXR
CCINTR
CCINTT
CCO2T
CCO2R
, V
, V
CCINT
CCINT
CCAUX
CCAUX
last for lowest overall power consumption (see the
last for lowest overall power consumption (see the
, and V
, and V
V
V
CCINT
CCAUX
Threshold for the V
Threshold for the V
Threshold for the V
Ramp rate from GND to valid V
Ramp rate from GND to valid V
Ramp rate from GND to valid V
CCO
CCO
level required to retain CMOS Configuration Latch (CCL) and RAM data
level required to retain CMOS Configuration Latch (CCL) and RAM data
supplies to the FPGA can be applied in any order. However, the FPGA configuration source (Platform Flash, SPI
supplies to the FPGA can be applied in any order. However, the FPGA configuration source (Platform Flash, SPI
CCINT
CCINT
, V
, V
CCO
CCO
CCINT
CCAUX
CCO
Bank 2, and V
Bank 2, and V
Bank 2 supply
Description
Description
supply
supply
CCINT
CCAUX
CCO
Description
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
Bank 2 supply level
CCAUX
CCAUX
supply level
supply level
UG331
UG331
supplies must rise through their respective threshold-voltage ranges with
supplies must rise through their respective threshold-voltage ranges with
chapter titled "Powering Spartan-3 Generation FPGAs" for more
chapter titled "Powering Spartan-3 Generation FPGAs" for more
Min
Min
0.4
1.0
1.0
0.2
0.2
0.2
Max
Max
100
100
100
1.0
2.0
2.0
Min
1.0
2.0
Units
Units
ms
ms
ms
Units
V
V
V
V
V
10