XC3S1200E-4FGG320C Xilinx Inc, XC3S1200E-4FGG320C Datasheet - Page 11
![IC SPARTAN-3E FPGA 1200K 320FBGA](/photos/6/72/67295/pk071-320_sml.jpg)
XC3S1200E-4FGG320C
Manufacturer Part Number
XC3S1200E-4FGG320C
Description
IC SPARTAN-3E FPGA 1200K 320FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1200E-4FGG320C
Number Of Logic Elements/cells
19512
Number Of Labs/clbs
2168
Total Ram Bits
516096
Number Of I /o
250
Number Of Gates
1200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
320-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1516
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S1200E-4FGG320C
Manufacturer:
FUJI
Quantity:
100
Company:
Part Number:
XC3S1200E-4FGG320C
Manufacturer:
XILINX
Quantity:
150
Company:
Part Number:
XC3S1200E-4FGG320C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S1200E-4FGG320C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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DS312-2 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
IDDRIN1
IDDRIN2
OTCLK1
OTCLK2
ICLK1
ICLK2
IDDRIN1/IDDRIN2 signals shown with dashed lines connect to the adjacent IOB in a differential pair only, not to the FPGA fabric.
All IOB control and output path signals have an inverting polarity option wihtin the IOB.
TCE
OCE
REV
IQ1
ICE
IQ2
T1
T2
SR
O1
O2
T
I
R
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
SR
SR REV
SR
SR REV
SR
SR REV
REV
REV
REV
Q
Q
Q
Q
Q
Q
Figure 5: Simplified IOB Diagram
TFF1
TFF2
OFF1
OFF2
IFF1
IFF2
Programmable
Programmable
www.xilinx.com
DDR
MUX
DDR
MUX
Delay
Delay
Three-state Path
Input Path
Output Path
Program-
Output
mable
Driver
Single-ended Standards
LVCMOS, LVTTL, PCI
Differential Standards
using V REF
Functional Description
Pull-Up
Down
Pull-
Keeper
Latch
DS312-2_19_110606
V
Pin
I/O Pin
from
Adjacent
IOB
ESD
ESD
V
REF
CCO
I/O
Pin
11
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