XC6SLX25-3CSG324C Xilinx Inc, XC6SLX25-3CSG324C Datasheet - Page 40
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XC6SLX25-3CSG324C
Manufacturer Part Number
XC6SLX25-3CSG324C
Description
IC FPGA SPARTAN 6 24K 324CSGBGA
Manufacturer
Xilinx Inc
Series
Spartan® 6 LXr
Specifications of XC6SLX25-3CSG324C
Number Of Logic Elements/cells
24051
Number Of Labs/clbs
1879
Total Ram Bits
958464
Number Of I /o
226
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-LFBGA, CSPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC6SLX25-3CSG324C
Manufacturer:
XILINX
Quantity:
329
Company:
Part Number:
XC6SLX25-3CSG324C
Manufacturer:
Xilinx Inc
Quantity:
10 000
CLB Switching Characteristics (SLICEM Only)
Table 39: CLB Switching Characteristics (SLICEM Only)
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Combinatorial Delays
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Sequential Delays
T
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
T
T
T
T
Set/Reset
T
T
T
F
AXCY
ILO
OPAB
ITO
TITO_LOGIC
OPCYA
OPCYB
OPCYC
OPCYD
BXCY
CXCY
DXCY
BYP
CINA
CINB
CINC
CIND
CKO
DICK
CECK
SRCK
CINCK
RPW
RQ
CEO
TOG
/T
/T
/T
Symbol
/T
CKDI
CKCE
CKSR
CKCIN
An – Dn LUT inputs to A to D outputs
An – Dn LUT inputs through F7AMUX/F7BMUX to
AMUX/CMUX output
An – Dn LUT inputs through F7AMUX or F7BMUX and F8MUX
to BMUX output
An – Dn LUT inputs through latch to AQ – DQ outputs
An – Dn LUT inputs to AQ – DQ outputs (latch as logic)
An LUT inputs to COUT output
Bn LUT inputs to COUT output
Cn LUT inputs to COUT output
Dn LUT inputs to COUT output
AX input to COUT output
BX input to COUT output
CX input to COUT output
DX input to COUT output
CIN input to COUT output
CIN input to AMUX output
CIN input to BMUX output
CIN input to CMUX output
CIN input to DMUX output
Clock to AQ – DQ outputs
AX – DX input to CLK on A – D flip-flops
CE input to CLK on A – D flip-flops
SR input to CLK on A – D flip-flops
CIN input to CLK on A – D flip-flops
SR input minimum pulse width
Delay from SR input to AQ – DQ flip-flops
Delay from CE input to AQ – DQ flip-flops
Toggle frequency (for export control)
Description
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
–0.07
–0.17
0.21
0.37
0.37
0.82
0.82
0.38
0.38
0.28
0.28
0.21
0.13
0.10
0.09
0.08
0.21
0.30
0.29
0.31
0.45
0.42
0.28
0.31
0.41
0.02
0.31
0.41
0.60
0.60
862
-3
–0.07
–0.13
Speed Grade
0.26
0.43
0.46
0.95
0.95
0.48
0.49
0.33
0.35
0.26
0.16
0.12
0.11
0.10
0.22
0.31
0.31
0.32
0.53
0.47
0.39
0.37
0.42
0.02
0.31
0.48
0.70
0.65
-3N
806
–0.07
–0.13
0.26
0.43
0.46
0.95
0.95
0.48
0.49
0.33
0.35
0.26
0.16
0.12
0.11
0.10
0.53
0.47
0.39
0.37
0.42
0.02
0.31
0.48
0.70
0.65
0.22
0.31
0.31
0.32
667
-2
–0.27
–0.29
–0.42
0.46
0.77
0.84
1.64
1.64
0.69
0.71
0.55
0.52
0.36
0.18
0.09
0.09
0.06
0.47
0.57
0.58
0.68
0.74
0.90
0.56
0.59
0.68
0.81
1.37
3.05
0.90
500
-1L
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Units
MHz
40