XC3S500E-5FGG320C Xilinx Inc, XC3S500E-5FGG320C Datasheet - Page 107
![IC FPGA SPARTAN-3E 500K 320-FBGA](/photos/6/72/67295/pk071-320_sml.jpg)
XC3S500E-5FGG320C
Manufacturer Part Number
XC3S500E-5FGG320C
Description
IC FPGA SPARTAN-3E 500K 320-FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S500E-5FGG320C
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
232
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
320-BGA
For Use With
122-1536 - KIT STARTER SPARTAN-3E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S500E-5FGG320C
Manufacturer:
Xilinx Inc
Quantity:
10 000
- Current page: 107 of 233
- Download datasheet (6Mb)
Start-Up
At the end of configuration, the FPGA automatically pulses
the Global Set/Reset (GSR) signal, placing all flip-flops in a
known state. After configuration completes, the FPGA
switches over to the user application loaded into the FPGA.
The sequence and timing of how the FPGA switches over is
programmable as is the clock source controlling the
sequence.
The default start-up sequence appears in
the Global Three-State signal (GTS) is released one clock
cycle after DONE goes High. This sequence allows the
DONE signal to enable or disable any external logic used
during configuration before the user application in the FPGA
starts driving output signals. One clock cycle later, the Glo-
bal Write Enable (GWE) signal is released. This allows sig-
nals to propagate within the FPGA before any clocked
storage elements such as flip-flops and block ROM are
enabled.
The function of the dual-purpose I/O pins
VS[2:0], HSWAP, and A[23:0]
DONE pin goes High. When DONE is High, these pins
become user I/Os. Like all user-I/O pins, GTS controls when
the dual-purpose pins can drive out.
DS312-2 (v3.8) August 26, 2009
Product Specification
R
,
also changes when the
,
Figure
such as M[2:0],
69, where
www.xilinx.com
The relative timing of configuration events is programmed
via the Bitstream Generator (BitGen) options in the Xilinx
development software. For example, the GTS and GWE
events can be programmed to wait for all the DONE pins to
High on all the devices in a multiple-FPGA daisy-chain, forc-
ing the FPGAs to start synchronously. Similarly, the start-up
sequence can be paused at any stage, waiting for selected
DCMs to lock to their respective input clock signals. See
also
By default, the start-up sequence is synchronized to CCLK.
Alternatively, the start-up sequence can be synchronized to
a user-specified clock from within the FPGA application
using the STARTUP_SPARTAN3E library primitive and by
setting the
FPGA application can optionally assert the GSR and GTS
signals via the STARTUP_SPARTAN3E primitive. For JTAG
configuration, the start-up sequence can be synchronized
to the TCK clock input.
Stabilizing DCM Clocks Before User
Start-Up Clock
Start-Up Clock
Figure 69: Default Start-Up Sequence
DONE
DONE
Phase
Phase
StartupClk
GWE
GWE
GTS
GTS
DONE High
0
0
bitstream generator option. The
1
1
Default Cycles
Sync-to-DONE
2
2
3
3
Functional Description
4
4
5
5
DS312-2_60_022305
Mode.
6 7
6 7
107
Related parts for XC3S500E-5FGG320C
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![XC3S500E-4FGG320C](/photos/6/72/67295/pk071-320_tmb.jpg)
Part Number:
Description:
IC SPARTAN-3E FPGA 500K 320FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC3S500E-4CPG132I](/photos/6/70/67095/pk373-cp132_tmb.jpg)
Part Number:
Description:
IC FPGA SPARTAN-3E 500K 132CSBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC3S500E-4PQG208I](/photos/6/71/67100/pq208_tmb.jpg)
Part Number:
Description:
IC FPGA SPARTAN-3E 500K 208-PQFP
Manufacturer:
Xilinx Inc
Datasheet:
![XC3S500E-4FTG256I](/photos/6/71/67101/pk053-256_tmb.jpg)
Part Number:
Description:
IC FPGA SPARTAN-3E 500K 256FTBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC3S500E-5FTG256C](/photos/6/71/67101/pk053-256_tmb.jpg)
Part Number:
Description:
IC FPGA SPARTAN-3E 500K 256FTBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC3S500E-4FGG320I](/photos/6/72/67295/pk071-320_tmb.jpg)
Part Number:
Description:
IC FPGA SPARTAN-3E 500K 320-FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC3S500E-4FG320I](/images/no-image3.png)
Part Number:
Description:
IC FPGA SPARTAN 3E 320FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC3S500E-4FTG256C](/photos/6/71/67101/pk053-256_tmb.jpg)
Part Number:
Description:
FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC3S500E-4PQ208I](/images/no-image3.png)
Part Number:
Description:
FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP
Manufacturer:
Xilinx Inc
Datasheet:
![XC3S500E-4PQG208C](/photos/6/71/67100/pq208_tmb.jpg)
Part Number:
Description:
FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP
Manufacturer:
Xilinx Inc
Datasheet:
![XC3S500E-4FT256I](/images/no-image3.png)
Part Number:
Description:
FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC3S500E-4CPG132C](/photos/6/70/67095/pk373-cp132_tmb.jpg)
Part Number:
Description:
FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 132-Pin CSBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC3S500E-4FG320C](/images/no-image3.png)
Part Number:
Description:
FPGA Spartan-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 320-Pin FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC3S500E-4VQG100I](/photos/6/70/67082/100-tqfp_tmb.jpg)
Part Number:
Description:
IC FPGA SPARTAN-3E 500K 100-VQFP
Manufacturer:
Xilinx Inc
Datasheet:
![XC3S500E-5CPG132C](/photos/6/70/67095/pk373-cp132_tmb.jpg)
Part Number:
Description:
IC FPGA SPARTAN-3E 500K 132CSBGA
Manufacturer:
Xilinx Inc
Datasheet: