XCS30XL-4TQG144C Xilinx Inc, XCS30XL-4TQG144C Datasheet - Page 44
![IC SPARTAN-XL FPGA 30K 144-TQFP](/photos/6/70/67094/144tqfp_sml.jpg)
XCS30XL-4TQG144C
Manufacturer Part Number
XCS30XL-4TQG144C
Description
IC SPARTAN-XL FPGA 30K 144-TQFP
Manufacturer
Xilinx Inc
Series
Spartan™-XLr
Datasheet
1.XCS05XL-4VQG100C.pdf
(83 pages)
Specifications of XCS30XL-4TQG144C
Number Of Logic Elements/cells
1368
Number Of Labs/clbs
576
Total Ram Bits
18432
Number Of I /o
113
Number Of Gates
30000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1297
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XCS30XL-4TQG144C
Manufacturer:
SIEMENS
Quantity:
2 000
Company:
Part Number:
XCS30XL-4TQG144C
Manufacturer:
XILINX
Quantity:
154
Part Number:
XCS30XL-4TQG144C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Spartan and Spartan-XL FPGA Families Data Sheet
Spartan Family CLB Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
44
Clocks
Combinatorial Delays
CLB Fast Carry Logic
Sequential Delays
Setup Time before Clock K
Hold Time after Clock K
Set/Reset Direct
Global Set/Reset
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
T
F
T
T
HH1CK
T
T
T
T
OPCY
T
HH1O
ASCY
ECCK
INCY
IHCK
DICK
MRW
SUM
RPW
MRQ
CKO
RCK
TOG
BYP
IHO
RIO
ICK
CH
ILO
CL
Clock High time
Clock Low time
F/G inputs to X/Y outputs
F/G inputs via H to X/Y outputs
C inputs via H1 via H to X/Y outputs
Operand inputs (F1, F2, G1, G4) to C
Add/Subtract input (F3) to C
Initialization inputs (F1, F3) to C
C
C
Clock K to Flip-Flop outputs Q
F/G inputs
F/G inputs via H
C inputs via H1 through H
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
All Hold times, all devices
Width (High)
Delay from C inputs via S/R, going High to Q
Minimum GSR pulse width
Delay from GSR input to any Q
Toggle Frequency (MHz)
(for export control purposes)
IN
IN
to C
through function generators to X/Y outputs
OUT
, bypass function generators
Description
OUT
OUT
OUT
www.xilinx.com
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan devices and
expressed in nanoseconds unless otherwise noted.
11.5
Min
3.0
3.0
1.8
2.9
2.3
1.3
2.0
2.5
0.0
3.0
See
-
-
-
-
-
-
-
-
-
-
-
page 50
-4
Max
166
1.2
2.0
1.7
1.7
2.8
1.2
2.0
0.5
2.1
3.0
Speed Grade
-
-
-
-
-
-
-
-
-
-
-
for T
RRI
values per device.
13.5
Min
4.0
4.0
2.4
3.9
3.3
2.0
2.6
4.0
0.0
4.0
-
-
-
-
-
-
-
-
-
-
-
-3
DS060 (v1.8) June 26, 2008
Max
125
Product Specification
1.6
2.7
2.2
2.1
3.7
1.4
2.6
0.6
2.8
4.0
-
-
-
-
-
-
-
-
-
-
-
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R