XA3S500E-4FTG256I Xilinx Inc, XA3S500E-4FTG256I Datasheet - Page 28
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XA3S500E-4FTG256I
Manufacturer Part Number
XA3S500E-4FTG256I
Description
IC FPGA SPARTAN-3E 500K 256FTBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3E XAr
Datasheet
1.XA3S100E-4VQG100I.pdf
(37 pages)
Specifications of XA3S500E-4FTG256I
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
190
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-LBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XA3S500E-4FTG256I
Manufacturer:
XILINX
Quantity:
7 208
Company:
Part Number:
XA3S500E-4FTG256I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 31: Switching Characteristics for the PS in Variable Phase Mode
Notes:
1.
2.
3.
Miscellaneous DCM Timing
Table 32: Miscellaneous DCM Timing
DS635 (v2.0) September 9, 2009
Product Specification
Notes:
1.
2.
3.
Phase Shifting Range
MAX_STEPS
FINE_SHIFT_RANGE_MIN
FINE_SHIFT_RANGE_MAX
DCM_RST_PW_MIN
DCM_RST_PW_MAX
DCM_CONFIG_LAG_TIME
The numbers in this table are based on the operating conditions set forth in
The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, i.e., the PHASE_SHIFT
attribute is set to 0.
The DCM_DELAY_STEP values are provided at the bottom of
This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
This specification is equivalent to the Virtex-4 DCM_RESET specification. This specification does not apply for Spartan-3E FPGAs.
This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3E FPGAs.
Symbol
R
Symbol
(2)
(1)
(2)
(3)
Maximum allowed number of DCM_DELAY_STEP
steps for a given CLKIN clock period, where T = CLKIN
clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE, double the clock
effective clock period.
Minimum guaranteed delay for variable phase shifting
Maximum guaranteed delay for variable phase shifting
Minimum duration of a RST pulse width
Maximum duration of a RST pulse width
Maximum duration from V
configuration successfully completed (DONE pin goes
High) and clocks applied to DCM DLL
Description
Table
www.xilinx.com
Description
27.
CCINT
Table 6
applied to FPGA
and
Table
30.
CLKIN < 60 MHz
CLKIN > 60 MHz
DCM_DELAY_STEP_MAX]
DCM_DELAY_STEP_MIN]
±[MAX_STEPS •
±[MAX_STEPS •
Min
N/A
N/A
N/A
N/A
3
±[INTEGER(10 •
±[INTEGER(15 •
(T
(T
CLKIN
CLKIN
Max
N/A
N/A
N/A
N/A
-
– 3 ns))]
– 3 ns))]
seconds
seconds
minutes
minutes
CLKIN
cycles
Units
Units
steps
steps
ns
ns
28