XCS30XL-4VQ100I Xilinx Inc, XCS30XL-4VQ100I Datasheet - Page 61

• Manufacturer Part Number: XCS30XL-4VQ100I
• Description: IC FPGA 3.3V I-TEMP HP 100VQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-XLr

Specifications of XCS30XL-4VQ100I

• Number Of Logic Elements/cells: 1368
• Number Of Labs/clbs: 576
• Total Ram Bits: 18432
• Number Of I /o: 77
• Number Of Gates: 30000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Spartan-XL Family IOB Output Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
DS060 (v1.8) June 26, 2008
Product Specification
Notes:
1.
2.
Propagation Delays
Setup and Hold Times
Global Set/Reset
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
OKPOF
T
Output timing is measured at ~50% V
rise/fall times are approximately two times longer than fast output rise/fall times.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
TSONF
OKFPF
SLOW
ECOK
OKEC
OFPF
TSHZ
MRW
OOK
OKO
OPF
RPO
R
Clock (OK) to Pad, fast
Output (O) to Pad, fast
3-state to Pad High-Z (slew-rate independent)
3-state to Pad active and valid, fast
Output (O) to Pad via Output Mux, fast
Select (OK) to Pad via Output Mux, fast
For Output SLOW option add
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
Clock Enable (EC) to clock (OK) setup time
Clock Enable (EC) to clock (OK) hold time
Minimum GSR pulse width
Delay from GSR input to any Pad
Description
CC
threshold, with 50 pF external capacitive loads including test fixture. Slew-rate limited output
www.xilinx.com
the simulation netlist. These path delays, provided as a
guideline, have been extracted from the static timing ana-
lyzer report. All timing parameters assume worst-case oper-
ating conditions (supply voltage and junction temperature).
Values are expressed in nanoseconds unless otherwise
noted.
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
Spartan and Spartan-XL FPGA Families Data Sheet
Device
10.5
Min
0.5
0.0
0.0
0.1
-
-
-
-
-
-
-
-
-
-
-
-
-5
Speed Grade
Max
11.9
12.4
12.9
13.9
14.9
3.2
2.5
2.8
2.6
3.7
3.3
1.5
-
-
-
-
-
11.5
Min
0.5
0.0
0.0
0.2
-
-
-
-
-
-
-
-
-
-
-
-
-4
Max
14.0
14.5
15.0
16.0
17.0
3.7
2.9
3.3
3.0
4.4
3.9
1.7
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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