XC3S400AN-4FGG400I Xilinx Inc, XC3S400AN-4FGG400I Datasheet - Page 40
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XC3S400AN-4FGG400I
Manufacturer Part Number
XC3S400AN-4FGG400I
Description
IC FPGA SPARTAN-3A 400K 400-FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3S50AN-4TQG144C.pdf
(2 pages)
3.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S400AN-4FGG400I
Total Ram Bits
368640
Number Of Logic Elements/cells
8064
Number Of Labs/clbs
896
Number Of I /o
311
Number Of Gates
400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
400-BGA
No. Of Logic Blocks
896
No. Of Gates
400000
No. Of Macrocells
8064
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
311
Clock
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S400AN-4FGG400I
Manufacturer:
TOSHIBA
Quantity:
198
Company:
Part Number:
XC3S400AN-4FGG400I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 29:
DS557 (v4.1) April 1, 2011
Product Specification
LVCMOS12
PCI33_3
PCI66_3
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
LVCMOS25 with 12 mA Drive
Following Signal Standard
Convert Output Time from
and Fast Slew Rate to the
(IOSTANDARD)
Output Timing Adjustments for IOB
QuietIO
Slow
Fast
2 mA
4 mA
6 mA
2 mA
4 mA
6 mA
2 mA
4 mA
6 mA
Adjustment Below
50.76
43.17
37.31
–
7.14
4.87
5.67
6.77
5.02
4.09
0.34
0.34
0.78
1.16
0.35
0.30
0.47
0.40
0.30
0.17
0.05
Speed Grade
-5
0
0
Add the
50.76
43.17
37.31
–
7.14
4.87
5.67
6.77
5.02
4.09
0.34
0.34
0.78
1.16
0.35
0.30
0.47
0.40
0.30
0.17
0.05
(Cont’d)
-4
0
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 29:
Notes:
1.
2.
3.
Differential Standards
LVDS_25
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
LVPECL_25
LVPECL_33
RSDS_25
RSDS_33
TMDS_33
PPDS_25
PPDS_33
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
LVCMOS25 with 12 mA Drive
Following Signal Standard
Convert Output Time from
and Fast Slew Rate to the
The numbers in this table are tested using the methodology
presented in
set forth in
These adjustments are used to convert output- and
three-state-path times originally specified for the LVCMOS25
standard with 12 mA drive and Fast slew rate to times that
correspond to other signal standards. Do not adjust times that
measure when outputs go into a high-impedance state.
Note that 16 mA drive is faster than 24 mA drive for the Slow slew
rate.
(IOSTANDARD)
Output Timing Adjustments for IOB
Table
Table 30
10,
Table
and are based on the operating conditions
13, and
Adjustment Below
Table
1.16
0.46
0.11
0.75
0.40
1.42
0.58
0.46
1.07
0.63
0.43
0.41
0.36
1.01
0.54
0.49
0.41
0.82
0.09
1.16
0.28
Speed Grade
-5
Add the
15.
Input Only
1.16
0.46
0.11
0.75
0.40
1.42
0.58
0.46
1.07
0.63
0.43
0.41
0.36
1.01
0.54
0.49
0.41
0.82
0.09
1.16
0.28
(Cont’d)
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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