XA3S500E-4CPG132Q Xilinx Inc, XA3S500E-4CPG132Q Datasheet - Page 34

• Manufacturer Part Number: XA3S500E-4CPG132Q
• Description: IC FPGA SPARTAN-3E 500K 132CSBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3E XAr

Specifications of XA3S500E-4CPG132Q

• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 92
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 132-TFBGA, CSPBGA
• Package: 132CSBGA
• Family Name: XA Spartan™-3E
• Device Logic Units: 10476
• Device System Gates: 500000
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 92
• Ram Bits: 368640
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Byte Peripheral Interface Configuration Timing
Table 42: Timing for BPI Configuration Mode
Table 43: Configuration Timing Requirements for Attached Parallel NOR Flash
DS635 (v2.0) September 9, 2009
Product Specification
Notes:
1.
2.
3.
T
T
T
T
T
T
T
T
T
(t
T
(t
T
(t
T
(t
t
FHQV
Symbol
Symbol
ACC
OE
CCLK1
CCLKn
MINIT
INITM
INITADDR
CCO
DCC
CCD
CE
ELQV
GLQV
AVQV
BYTE
FLQV,
These requirements are for successful FPGA configuration in BPI mode, where the FPGA provides the CCLK frequency. The post
configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source.
Subtract additional printed circuit board routing delay as required by the application.
The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor
value also depends on whether the FPGA’s HSWAP pin is High or Low.
)
)
)
)
R
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on CSI_B, RDWR_B, and M[2:0] mode pins before the rising
edge of INIT_B
Hold time on CSI_B, RDWR_B, and M[2:0] mode pins after the rising
edge of INIT_B
Minimum period of initial A[23:0] address cycle;
LDC[2:0] and HDC are asserted and valid
Address A[23:0] outputs valid after CCLK falling edge
Setup time on D[7:0] data inputs before CCLK rising edge
Hold time on D[7:0] data inputs after CCLK rising edge
Parallel NOR Flash PROM chip-select
time
Parallel NOR Flash PROM
output-enable time
Parallel NOR Flash PROM read access
time
For x8/x16 PROMs only: BYTE# to
output valid time
Description
(3)
Description
www.xilinx.com
T
ACC
≤
0.5T
(M[2:0]=<0:1:0>)
(M[2:0]=<0:1:1>)
CCLKn min
BPI-DN:
BPI-UP:
T
T
T
BYTE
CE
OE
Requirement
(
≤
≤
≤
T
T
)
T
INITADDR
INITADDR
–
INITADDR
T
Minimum
CCO
50
0
5
2
–
T
(see
(see
See
See
See
DCC
Maximum
Table
Table
Table 38
Table 38
Table 38
–
PCB
5
2
-
-
34)
34)
T
cycles
Units
Units
CCLK1
ns
ns
ns
ns
ns
ns
34