XA3S500E-4CPG132I Xilinx Inc, XA3S500E-4CPG132I Datasheet - Page 16

• Manufacturer Part Number: XA3S500E-4CPG132I
• Description: IC FPGA SPARTAN-3E 500K 132CSBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3E XAr

Specifications of XA3S500E-4CPG132I

• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 92
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 132-TFBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 15: Setup and Hold Times for the IOB Input Path
DS635 (v2.0) September 9, 2009
Product Specification
Notes:
1.
2.
3.
Setup Times
T
T
Hold Times
T
T
Set/Reset Pulse Width
T
Symbol
IOPICK
IOPICKD
IOICKP
IOICKPD
RPW_IOB
The numbers in this table are tested using the methodology presented in
Table 6
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from
These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from
edge.
and
R
Time from the setup of data at the Input
pin to the active transition at the ICLK input
of the Input Flip-Flop (IFF). No Input Delay
is programmed.
Time from the setup of data at the Input
pin to the active transition at the IFF’s ICLK
input. The Input Delay is programmed.
Time from the active transition at the IFF’s
ICLK input to the point where data must be
held at the Input pin. No Input Delay is
programmed.
Time from the active transition at the IFF’s
ICLK input to the point where data must be
held at the Input pin. The Input Delay is
programmed.
Minimum pulse width to SR control input
on IOB
Table
9.
Description
Table
Table
17.
17. When the hold time is negative, it is possible to change the data before the clock’s active
LVCMOS25
IFD_DELAY_VALUE = 0
LVCMOS25
IFD_DELAY_VALUE =
default software setting
LVCMOS25
IFD_DELAY_VALUE = 0
LVCMOS25
IFD_DELAY_VALUE =
default software setting
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Conditions
(2)
(2)
(2)
(2)
,
,
,
,
Table 19
and are based on the operating conditions set forth in
DELAY_
VALUE
IFD_
0
2
3
2
5
4
0
2
3
2
5
4
XA3S100E
XA3S250E
XA3S500E
XA3S1200E
XA3S1600E
XA3S100E
XA3S250E
XA3S500E
XA3S1200E
XA3S1600E
Device
All
All
All
Speed
Grade
–0.76
–3.93
–3.51
–3.74
–4.30
–4.14
2.12
6.49
6.85
7.01
8.67
7.69
1.80
Min
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16