XC2S50E-6PQ208C Xilinx Inc, XC2S50E-6PQ208C Datasheet - Page 25

• Manufacturer Part Number: XC2S50E-6PQ208C
• Description: IC FPGA 1.8V 384 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-IIEr

Specifications of XC2S50E-6PQ208C

• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 384
• Total Ram Bits: 32768
• Number Of I /o: 146
• Number Of Gates: 50000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Case: QFP208
• Dc: 03+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1205

Slave Serial Mode
In Slave Serial mode, the FPGA’s CCLK pin is driven by an
external source, allowing the FPGA to be configured from
other logic devices such as microprocessors or in a
daisy-chain configuration.
a Master Serial FPGA configuring a Slave Serial FPGA
Notes:
1.
DS077-2 (v2.3) June 18, 2008
Product Specification
PROGRAM
Figure 18: Loading Serial Mode Configuration Data
If the DriveDone configuration option is not active for any of the FPGAs, pull up DONE with a 330
R
CCLK Rising Edge
To CRC Check
M2
PROGRAM
DONE
User Load One
(Master Serial)
Configuration
Configuration
M0 M1
Goes High
Bit on Next
After INIT
Data File?
Spartan-IIE
End of
Figure 19
GND
Figure 19: Master/Slave Serial Configuration Circuit Diagram
Yes
DOUT
V
V
CCLK
3.3V
CCO
CCINT
INIT
DIN
shows connections for
No
DS001_14_032300
1.8V
3.3V
3.3 K
www.xilinx.com
CLK
DATA
CE
RESET/OE
from a PROM. A Spartan-IIE device in slave serial mode
should be connected as shown for the third device from the
left. Slave Serial mode is selected by a <11x> on the mode
pins (M0, M1, M2). The weak pull-ups on the mode pins
make slave serial the default mode if the pins are left uncon-
nected.
The serial bitstream must be setup at the DIN input pin a
short time before each rising edge of an externally gener-
ated CCLK.
Timing for Slave Serial mode is shown in
page
Daisy Chain
Multiple FPGAs in Slave Serial mode can be daisy-chained
for configuration from a single source. After an FPGA is
configured, data for the next device is sent to the DOUT pin.
Data on the DOUT pin changes on the rising edge of CCLK.
Note that DOUT changes on the falling edge of CCLK for
some Xilinx families but mixed daisy chains are allowed.
Configuration must be delayed until INIT pins of all
daisy-chained FPGAs are High. For more information, see
Start-up, page
The maximum amount of data that can be sent to the DOUT
pin for a serial daisy chain is 2
or 33,554,400 bits, which is approximately 8 XC2S600E bit-
streams. The configuration bitstream of downstream
devices is limited to this size.
PROM
Xilinx
GND
49.
Spartan-IIE FPGA Family: Functional Description
CEO
3.3V
V
CC
23.
M2
DIN
CCLK
PROGRAM
DONE
M0 M1
Ω
Spartan-IIE
20
resistor.
(Slave)
-1 (1,048,575) 32-bit words,
GND
V
V
3.3V
DOUT
CCO
CCINT
INIT
1.8V
DS077-2_04_061708
Figure 24,
25