XC3S50-5TQG144C Xilinx Inc, XC3S50-5TQG144C Datasheet - Page 96

• Manufacturer Part Number: XC3S50-5TQG144C
• Description: SPARTAN-3A FPGA 50K 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S50-5TQG144C

• Total Ram Bits: 73728
• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 192
• Number Of I /o: 97
• Number Of Gates: 50000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-LQFP
• No. Of Logic Blocks: 1728
• No. Of Gates: 50000
• No. Of Macrocells: 1728
• No. Of Speed Grades: 5
• No. Of I/o's: 97
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 67: Timing for the JTAG Test Access Port
96
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
T
Hold Times
T
T
Clock Timing
T
T
F
TCKTDO
TDITCK
TMSTCK
TCKTDI
TCKTMS
TCKH
TCKL
TCK
The numbers in this table are based on the operating conditions set forth in
Symbol
TCK
TMS
TDI
TDO
(Input)
(Input)
(Input)
(Output)
The time from the falling transition on the TCK pin to data
appearing at the TDO pin
The time from the setup of data at the TDI pin to the rising
transition at the TCK pin
The time from the setup of a logic level at the TMS pin to the
rising transition at the TCK pin
The time from the rising transition at the TCK pin to the point
when data is last held at the TDI pin
The time from the rising transition at the TCK pin to the point
when a logic level is last held at the TMS pin
TCK pin High pulse width
TCK pin Low pulse width
Frequency of the TCK signal
T
TDITCK
T
TMSTCK
Figure 37: JTAG Waveforms
Description
www.xilinx.com
T
TCKTDI
T
TCKTMS
JTAG Configuration
Boundary-Scan
Table
T
TCKTDO
31.
T
CCH
All Speed Grades
1/F
Min
1.0
7.0
7.0
DS099-3 (v2.5) December 4, 2009
0
0
5
5
0
0
TCK
T
CCL
Product Specification
Max
11.0
DS099_06_102909
33
25
∞
∞
-
-
-
-
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
R